HB52F328EM-75B Datasheet, PDF (1/19 Pages) Elpida Memory – 256MB Unbuffered SDRAM DIMM

DATA SHEET
256MB Unbuffered SDRAM DIMM
HB52F328EM-75B (32M words × 64 bits, 1 bank)
HB52F329EM-75B (32M words × 72 bits, 1 bank)
Description
The HB52F328EM and HB52F329EM belong to 8-byte
DIMM (Dual In-line Memory Module) family, and have
been developed as an optimized main memory solution
for 8-byte processor applications. They are
synchronous Dynamic RAM Module, mounted 256M
bits SDRAMs (HM5225805BTT) sealed in TSOP
package, and 1 piece of serial EEPROM (2k bits) for
Presence Detect (PD). The HB52F328EM is organized
32M × 64 × 1 bank mounted 8 pieces of 256M bits
SDRAM. The HB52F329EM is organized 32M × 72 × 1
bank mounted 9 pieces of 256M bits SDRAM.
Therefore, they make high density mounting possible
without surface mount technology. They provide
common data inputs and outputs. Decoupling
capacitors are mounted beside each TSOP on the
module board.
• 2 variations of refresh
 Auto refresh
 Self refresh
Features
• Fully compatible with: JEDEC standard outline 8-
byte DIMM
• 168-pin socket type package (dual lead out)
 Outline: 133.37mm (Length) × 34.925mm (Height)
× 4.00mm (Thickness)
 Lead pitch: 1.27mm
• 3.3V power supply
• Clock frequency: 133MHz (max.)
• LVTTL interface
• Data bus width : × 64 Non parity (HB52F328EM)
: × 72 ECC (HB52F329EM)
• Single pulsed /RAS
• 4 Banks can operates simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8
• 2 variations of burst sequence
 Sequential
 Interleave
• Programmable /CE latency (CL) : 3 (133MHz)
: 2 (100MHz)
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64ms
Document No. E0184H10 (Ver. 1.0)
Date Published June 2001
Printed in Japan
URL: http://www.elpida.com
C Elpida Memory, Inc. 2001
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.