HB56UW873E-F Datasheet, PDF (12/27 Pages) Elpida Memory – 64MB Buffered EDO DRAM DIMM 8-Mword × 72-bit, 4k Refresh, 1 Bank Module (9 pcs of 8M × 8 components)

HB56UW873E-F
19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained.
When output buffer is turned on and off within a very short time, generally it causes large V_CC/V_SS line
noise, which causes to degrade V_IH min/V_IL max level.
20. t_HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read
cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode
mix cycle (1), (2)), minimum value of CAS cycle (t_CAS + t_CP + 2 t_T) becomes greater than the specified
t_HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode
mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time
and turn off time are specified by the timing specifications of later rising edge of RAS and CAS
between t_OHR and t_OH and between t_OFR and t_OFF.
22. t_DOH defines the time at which the output level go cross. V_OL = 0.8 V, V_OH = 2.0 V of output timing
reference level.
23. XXX: H or L (H: V_IH (min) ≤ V_IN ≤ V_IH (max), L: V_IL (min) ≤ V_IN ≤ V_IL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied V_IH or V_IL.
Data Sheet E0102H10
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