HB56UW873E-F Datasheet, PDF (11/27 Pages) Elpida Memory – 64MB Buffered EDO DRAM DIMM 8-Mword × 72-bit, 4k Refresh, 1 Bank Module (9 pcs of 8M × 8 components)

HB56UW873E-F
EDO Page Mode Read-Modify-Write Cycle
Parameter
EDO page mode read- modify-write
cycle time
WE delay time from CAS precharge
50 ns
Symbol Min
t _HPRWC
57
Max
—
t _CPW
45
—
60 ns
Min Max
68
—
54
—
Unit Notes
ns
ns 14
Refresh
Parameter
Symbol
Max
Unit
Notes
Refresh period
t _REF
64
ms
4096 cycles
Notes: 1. AC measurements assume t_T = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the t_RCD (max) limit insures that t_RAC (max) can be met, t_RCD (max) is specified as a
reference point only; if t_RCD is greater than the specified t_RCD (max) limit, than the access time is
controlled exclusively by t_CAC.
4. Operation with the t_RAD (max) limit insures that t_RAC (max) can be met, t_RAD (max) is specified as a
reference point only; if t_RAD is greater than the specified t_RAD (max) limit, then access time is controlled
exclusively by t_AA.
5. Either t_OED or t_CDD must be satisfied.
6. Either t_DZO or t_DZC must be satisfied.
7. V_IH (min) and V_IL (max) are reference levels for measuring timing of input signals. Also, transition times
are measured between V_IH (min) and V_IL (max).
8. Assumes that t_RCD ≤ t_RCD (max) and t_RAD ≤ t_RAD (max). If t_RCD or t_RAD is greater than the maximum
recommended value shown in this table, t_RAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that t_RCD ≥ t_RCD (max) and t_RCD + t_CAC (max) ≥ t_RAD + t_AA (max).
11. Assumes that t_RAD ≥ t_RAD (max) and t_RCD + t_CAC (max) ≤ t_RAD + t_AA (max).
12. Either t_RCH or t_RRH must be satisfied for a read cycles.
13. t_OFF (max), t_OEZ (max), t_WEZ (max) and t_OFR (max) define the time at which the outputs achieve the open
circuit condition and are not referred to output voltage levels.
14. t_WCS, t_RWD, t_CWD, t_AWD and t_CPW are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if t_WCS ≥ t_WCS (min), the cycle is an early write cycle and the data
out pin will remain open circuit (high impedance) throughout the entire cycle; if t_RWD ≥ t_RWD (min), t_CWD ≥
t_CWD (min), and t_AWD ≥ t_AWD (min), or t_CWD ≥ t_CWD (min), t_AWD ≥ t_AWD (min) and t_CPW ≥ t_CPW (min), the cycle isa
read-modify-write and the data output will contain data read from the selected cell; if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
15. t_DS and t_DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed
write or read-modify-write cycles.
16. t_RASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among t_AA, t_CAC and t_CPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
Data Sheet E0102H10
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