E981.07 Datasheet, PDF (25/46 Pages) ELMOS Semiconductor AG – Two independent operating channels

Two Channel Sensor Interface PSI5
ADVANCE PRODUCT INFORMATION JUL 26, 2011
5.2.2 Functional Description
E981.07
The MCU and the 981.07 are communicating over an SPI bus in a master-slave operation mode. The MCU acts
always as master and transmits commands over the MOSI (Master Out Slave In) line. The 981.07 acts always
as slave and sends back status or RSU data to the MCU over the MISO (Master In Slave Out) line.
5.2.3 SPI Communication
The data transfer between the MCU and 981.07 is done serially with a four wire system:
Signal
Description
Direction
MOSI
Master Out Slave In
MCU
⇒ 981.07
MISO
Master In Slave Out
981.07 ⇒ MCU
SCK
Serial Clock
MCU
⇒ 981.07
CSB
Chip Select (low active)
MCU
⇒ 981.07
Bits are transmitted simultaneously to (MOSI) and from (MISO) the 981.07 when CSB is active (LOW) and each
bit is synchronised by the clock SCK. The responses are transferred to the MCU in a single-stage pipeline
fashion, where the response for a given request is transmitted in the frame immediately following the request as
shown below in Figure 5.2-2.
Commands received during the transmission are executed by the 981.07 on the rising edge of CSB. Only
commands with 16 clock cycles are executed.
Each transmission starts with a falling edge on CSB and ends with the rising edge. During the transmission
command and data shift are controlled by SCK and CSB according to the following rules:
• Frame size is 16 bits
• Commands and data are shifted MSB first, LSB last
• Each bit is sampled on the rising edge of SCK (MOSI line)
• Each RSU-data-/status-bits is shifted out on the falling edge of SCK (MISO line)
• MISO becomes active during CSB='0' and is tristate during CSB='1'
Incoming commands are validated on the rising edge of CSB and executed in case that 16 clock cycles are
counted during the transmission, glitches at CSB do not lead to a re-execution of the previous command.
The SPI is reset in case of power-on-reset or external reset.
The response on MISO to the first command after external reset or internal reset is a non-sensor data error
response with RE bit is set, and the DU bit is cleared (RE=1, DU=0).
Figure 5.2-2: SPI Response Latency
ELMOS Semiconductor AG
Data Sheet 25 / 45
QM-No.: 25DS0050E.00
This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.