E981.07 Datasheet, PDF (15/46 Pages) ELMOS Semiconductor AG – Two independent operating channels

Two Channel Sensor Interface PSI5
ADVANCE PRODUCT INFORMATION JUL 26, 2011
4.2 AC Parameter
E981.07
4.2.1 Channel Interface Parameters
No.
Parameter
Symbol
Condition
Min. Typ. Max. Unit
1a Interface (high/low- tSAT_OC_SDEL_ST
side) over current
start up delay
standard mode (SV=0) ➂
5.12
-TCLK
5.12
5.12 ms
+TCLK
1b Interface (high/low
tSAT_OC_SDEL_IN
side) over current
start up delay
increased mode (SV=1) ➂
10.24 10.24 10.24 ms
-TCLK
+TCLK
2a Interface high side
over current shut
down delay
tSAT_OC_ODEL_ST
standard mode (SV=0) ➂
short to GND
512
-TCLK
512 512 μs
+TCLK
2b Interface high side
over current shut
down delay
tSAT_OC_ODEL_IN
increased mode (SV=1) ➂
short to GND
10.24 10.24 10.24 ms
-TCLK
+TCLK
3
Interface low side
tSAT_OC_ODEL_LS
short to battery ➂
over current shut
down delay
512
-TCLK
512 512 µs
+TCLK
4
Data detection delay tSAT_TH_DEL_DELTA ➁
difference between
negative and positive
edge
-
-
250 ns
5 Sync pulse delay
first slot
tSAT_Sync_Delay
See figure 5.1-6, ①
2.0
-
4
µs
6 Sync pulse jitter
tjitter
See figure 5.1-6, ➁ ➂
0
-
250 ns
7
REXT out of range tOOR_DEB
debouncing
-
512
-
µs
8a VBUS/VSYNC too
low delay
8b VBUS/VSYNC too
low delay
after power-on reset,
depends on internal clock
fOSC_ (see 4.2.4.1)
0.57 0.85 2.0 ms
interface operating, depends
-
32
-
µs
on external clock CLK (see
3.2.1.8)
① The parameter tSAT_Sync_Delay will be measured from the rising edge of the SAT_SYNC signal (t ) SAT_Sync_start until
the voltage at SATFDX is equal Vt0 (Vt0=VSATFDX+0.5V). See figures 5.1-4 and 5.1-6 .
➁Not tested in production
➂ T_CLK= 250 ns plus external clock tolerance
ELMOS Semiconductor AG
Data Sheet 15 / 45
QM-No.: 25DS0050E.00
This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice.