DS4550 Datasheet, PDF (9/18 Pages) Dallas Semiconductor – I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

I²C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
Slave Address and Address Pins
The DS4550’s I²C slave address is determined by the
state of the A0, A1, and A2 address pins as shown in
Figure 2. Address pins connected to GND result in a ‘0’
in the corresponding bit position in the slave address.
Conversely, address pins connected to V_CC result in a
‘1’ in the corresponding bit positions. I²C communica-
tion is described in detail in a later section.
MSB
LSB
1 0 1 0 A2 A1 A0 R/W
SLAVE
ADDRESS*
*THE SLAVE ADDRESS IS DETERMINED BY
ADDRESS PINS A0, A1, AND A2.
READ/WRITE
BIT
IEEE 1149.1 JTAG Operation
The DS4550 contains an IEEE 1149.1 compliant JTAG
port in addition to the I²C serial bus. Either can be used
to access the internal memory. However, the device
contains no bus arbitration and hence both busses
cannot be used at the same time. All of the I/O pins on
the DS4550 are IEEE 1149.1 boundary-scan compliant.
I/O_0 to I/O_8 as well as the I²C port pins, contain the
typical JTAG boundary scan cells, which allow the pins
to be polled or forced high/low using standard JTAG
instructions. The DS4550 also contains some exten-
sions to normal JTAG functionality, which allows access
to the internal memory. In particular, the DS4550 has
three device-specific test data registers (Memory
Address, Memory Read, and Memory Write) and three
device-specific instructions (ADDRESS, READ, and
WRITE), which provide memory access.
Figure 2. DS4550 I²C Slave Address Byte
EEPROM
MSB
TEST REGISTERS
LSB
MEMORY ADDRESS REGISTER
[LENGTH = 8 BITS]
MEMORY READ REGISTER
[LENGTH = 8 BITS]
MEMORY WRITE REGISTER
[LENGTH = 8 BITS]
BOUNDARY SCAN REGISTER
[LENGTH = 33 BITS]
IDENTIFICATION REGISTER
[LENGTH = 32 BITS]
BYPASS REGISTER
[LENGTH = 1 BIT]
MUX 1
V_CC V_CC
R_JPU
R_JPU
TDI
TMS
TCK
INSTRUCTION REGISTER
[LENGTH = 4 BITS]
MSB
LSB
TEST ACCESS PORT
(TAP) CONTROLLER
MUX 2
TDO
Figure 3. DS4550 JTAG Block Diagram
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