DS4550 Datasheet, PDF (7/18 Pages) Dallas Semiconductor – I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

I²C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
Block Diagram
V_CC
V_CC
SDA
BSC
SCL
BSC
I²C
A0
BSC
INTERFACE
A1
BSC
A2
BSC
V_CC
EEPROM
64 BYTES
USER
MEMORY
R_JPU
R_JPU
TMS
TDI
JTAG
CONTROL
TDO
PORT
TCK
GND
I/O CONTROL
REGISTERS
PULLUP ENABLE (F0h-F1h)
I/O CONTROL (F2h-F3h)
DS4550
I/O CELL
BSC
V_CC (x9)
R_PU
BSC
I/O_n
[n = 0 TO 8]
I/O STATUS (F8h-F9h)
BSC
BOUNDARY SCAN CELL (BSC)
Detailed Description
The DS4550 contains nine bidirectional, NV, input/out-
put (I/O) pins, and a 64-byte EEPROM user memory.
The I/O pins and user memory are accessible through
either the I²C compatible serial bus or the IEEE 1149.1
JTAG interface.
Programmable NV I/O Pins
Each programmable I/O pin consists of an input and an
open-collector output with a selectable internal pullup
resistor. To enable the pullups for each I/O pin, write to
the Pullup Enable Registers (F0h and F1h). To pull the
output low or place the pulldown transistor into a high-
impedance state, write to the I/O Control Registers (F2h
and F3h). To read the voltage levels present on the I/O
pins, read the I/O Status Registers (F8h and F9h). To
determine the status of the output register, read the I/O
Control Registers and the Pullup Resistor Registers.
The I/O Control Registers and the Pullup Enable
Registers are all SRAM-shadowed EEPROM registers.
It is possible to disable the EEPROM writes of the regis-
ters using the SEE bit in the Configuration Register.
This reduces the time required to write to the register
and increases the amount of times the I/O pins can be
adjusted before the EEPROM is worn out.
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