DS4550 Datasheet, PDF(4/18 Page) Dallas Semiconductor – I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

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DS4550 Datasheet, PDF (4/18 Pages) Dallas Semiconductor – I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

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I2C and JTAG Nonvolatile 9-Bit I/O

Expander Plus Memory

NONVOLATILE MEMORY CHARACTERISTICS

(VCC = +2.7V to +5.5V, unless otherwise noted.)

PARAMETER

EEPROM Writes

SYMBOL

CONDITIONS

+70Â°C (Note 3)

MIN TYP

50,000

MAX UNITS

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

Note 9:

All voltages referenced to ground.

ISTBY is specified with SDA = SCL = TMS = TDI = VCC, outputs floating, and inputs connected to VCC or GND.

Guaranteed by design.

Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard mode timing.

After this period, the first clock pulse is generated.

CBï£§total capacitance of one bus line in picofarads.

EEPROM write time applies to all the EEPROM memory and SRAM-shadowed EEPROM memory when SEE = 0. The

EEPROM write time begins after a stop condition occurs.

TCK can be stopped either high or low.

EEPROM write begins immediately after the UPDATE-DR state that latches the data to be written. The EEPROM cannot be

accessed until the EEPROM write has completed. However, the remainder of the JTAG functionality is active and accessi-

ble during the EEPROM write.

TCK

TDI, TMS

TDO

Figure 1. JTAG Timing Diagram

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