DS4550 Datasheet, PDF (13/18 Pages) Dallas Semiconductor – I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

I²C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
Table 3. Boundary Scan Control Bits [33 Bits]
CELL
NUMBER
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NAME
A2 input
A1 input
A0 input
SCL input
SDA input
SDA output
IO8 pubout
IO8 pdbout
IO8 input
IO7 pubout
IO7 pdbout
IO7 input
IO6 pubout
IO6 pdbout
IO6 input
IO5 pubout
IO5 pdbout
TYPE
Input Observe Only
Input Observe Only
Input Observe Only
Input Observe Only
Input Observe Only
Output
Output
Output
Input Observe Only
Output
Output
Input Observe Only
Output
Output
Input Observe Only
Output
Output
CELL
NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
IO5 input
IO4 pubout
IO4 pdbout
IO4 input
IO3 pubout
IO3 pdbout
IO3 input
IO2 pubout
IO2 pdbout
IO2 input
IO1 pubout
IO1 pdbout
IO1 input
IO0 pubout
IO0 pdbout
IO0 input
TYPE
Input Observe Only
Output
Output
Input Observe Only
Output
Output
Input Observe Only
Output
Output
Input Observe Only
Output
Output
Input Observe Only
Output
Output
Input Observe Only
Table 4. EEPROM Read Cycle
STEP
Select
Address
Register
Load
EEPROM
Address
Select
Read
Register
Read
EEPROM
Data
TAP STATE
Select-IR-Scan
Capture-IR
Shift-IR (4 x TCK)
Exit1-IR
Update-IR
Select-DR-Scan
Capture-DR
Shift-DR (8 x TCK)
Exit1-DR
Update-DR
Select-IR-Scan
Capture-IR
Shift-IR (4 x TCK)
Exit1-IR
Update-IR
Select-DR-Scan
Capture-DR
Shift-DR (8 x TCK)
Exit1-DR
Update-DR
COMMENTS


The 4-bit instruction is shifted in through TDI.



No-op.
The 8-bit address is shifted in through TDI.

The shifted 8-bit Address Register data is output latched.


The 4-bit instruction is shifted in through TDI.



The 8-bit EEPROM data is loaded into the EEPROM Read Register.
The 8-bit data is shifted out through TDO.

No-op.
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