DS4550 Datasheet, PDF (8/18 Pages) Dallas Semiconductor – I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

I²C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
Memory Map and Memory Types
The DS4550 memory map is shown in Table 1. Three
different types of memory are present in the DS4550:
EEPROM, SRAM-shadowed EEPROM, and SRAM.
Memory locations specified as EEPROM are NV.
Writing to these locations results in an EEPROM write
cycle for a time specified by t_WR in the AC Electrical
Characteristics table. Locations specified as SRAM-
shadowed EEPROM can be configured to operate in
one of two modes specified by the SEE bit (the LSB of
the Configuration Register, F4h). When the SEE bit = 0
(default), the memory location acts like EEPROM.
However, when SEE = 1, shadow SRAM is written to
instead of the EEPROM. This eliminates both the EEP-
ROM write time, t_WR, as well as the concern of wearing
out the EEPROM. This is ideal for applications that wish
to constantly write to the I/Os. Power-up default states
can be programmed for the I/Os in EEPROM (with SEE
= 0) and then once powered up, SEE can be written to
a 1 so that the I/Os can be updated periodically in
SRAM. The final type of memory present in the DS4550
is standard SRAM.
Table 1. DS4550 Memory Map
ADDRESS
TYPE
NAME
FUNCTION
00h to 3Fh
40 to E7h
E8 to EFh
F0h
F1h
F2h
F3h
F4h
F5h to F7h
F8h
F9h
FAh to FFh
EEPROM User Memory 64 Bytes of General-Purpose User EEPROM.

Reserved
Undefined Address Space for Future Expansion. Reads and writes to
this space will have no affect on the device.
EEPROM
Reserved
Pullup Enable
0

Pullup Enable for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the
MSB. Set the corresponding bit to enable the pullup; clear the bit to
disable the pullup.
Pullup Enable
1
Pullup Enable for I/O_8. I/O_8 is the LSB. Only the LSB is used. Set
the LSB bit to enable the pullup on I/O_8; clear the LSB to disable the
pullup.
SRAM
Shadowed
EEPROM
I/O Control 0
[EEPROM
writes are
disabled if
the SEE bit
= 1]
I/O Control 1
I/O Control for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the MSB.
Clearing the corresponding bit of the register pulls the selected I/O
pin low; setting the bit places the pulldown transistor into a high-
impedance state. When the pulldown is high impedance, the output
will float if no pullup/down is connected to the pin.
I/O Control for I/O_8. I/O_8 is the LSB. Only the LSB is used. Clearing
the LSB of the register pulls the I/O_8 pin low; setting the LSB will
place the pulldown transistor into a high-impedance state. When the
pulldown is high impedance, the output will float if no pullup/down is
connected to the pin.
Configuration
User Memory
Configuration Register. The LSB is the SEE bit. When set, this bit
disables writes to the EEPROM; writing only effects the shadow
SRAM. When set to 0, both the EEPROM and the shadow SRAM is
written
3 bytes of General-Purpose User EEPROM
I/O Status 0
I/O Status for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the MSB.
Writing to this register has no effect. Read this register to determine
the state of the I/O_0 to I/O_7 pins.
SRAM
I/O Status 1
I/O Status for I/O_8. I/O_8 is the LSB. Only the LSB is used; the other
bits could be any value when read. Writing to this register has no
effect. Read this register to determine the state of the I/O_8 pin.
SRAM User
Memory
6 Bytes of General-Purpose SRAM
FACTORY
DEFAULT
00h


00h
00h
FFh
01h
00h
00h



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