DS4550 Datasheet, PDF (15/18 Pages) Dallas Semiconductor – I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory

I²C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
Bit Read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time (see Figure 5) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses including when it is reading bits from
the slave.
Acknowledgement (ACK and NACK): An
Acknowledgement (ACK) or Not Acknowledge (NACK)
is always the 9th bit transmitted during a byte transfer.
The device receiving data (the master during a read or
the slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 5) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used
to terminate a read sequence or as an indication that
the device is not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8-bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minated communication so the slave returns control of
the SDA to the master.
Slave Address Byte: Each slave on the I²C bus
responds to a slave address byte sent immediately fol-
lowing a start condition. The slave address byte con-
tains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
SDA
t_BUF
t_LOW
t_R
t_F
SCL
t_HD:STA
t_HIGH
STOP
START
t_HD:DAT
NOTE: TIMING IS REFERENCED TO V_IL(MAX) AND V_IH(MIN)
t_SU:DAT
Figure 5. I²C Timing Diagram
t_HD:STA
t_SU:STA
REPEATED
START
t_SP
t_SU:STO
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