DS1375 Datasheet, PDF (9/11 Pages) Dallas Semiconductor – 2-Wire Digital Input RTC with Alarm

2-Wire Digital Input RTC with Alarm
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Status Register (0Fh)
Bit 1/Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag
bit indicates that the time matched the alarm 2 regis-
ters. If the A2IE bit is logic 1 and the INTCN bit is set to
logic 1, the SQW/INT pin is also asserted. A2F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
Bit 0/Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag
bit indicates that the time matched the alarm 1 regis-
ters. If the A1IE bit is logic 1 and the INTCN bit is set to
logic 1, the SQW/INT pin is also asserted. A1F is
cleared when written to logic 0. This bit can only be
written to logic 0. Attempting to write to logic 1 leaves
the value unchanged.
2-Wire Serial Data Bus
The DS1375 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The device that controls
the message is called a master. The devices that are
controlled by the master are slaves. A master device
that generates the serial clock (SCL), controls the bus
access, and generates the START and STOP condi-
tions must control the bus. The DS1375 operates as a
slave on the 2-wire bus. Connections to the bus are
made through the open-drain I/O lines SDA and SCL.
Within the bus specifications a standard mode (100kHz
max clock rate) and a fast mode (400kHz max clock
rate) are defined. The DS1375 works in both modes.
Bit 3
0
Bit 2
0
Bit 1
A2F
Bit 0
A1F
The following bus protocol has been defined (Figure 3):
• Data transfer can be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high can be
interpreted as control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
Start data transfer: A change in the data line’s
state from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the data line’s
state from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The data line’s state represents valid
data when, after a START condition, the data line is
stable for the duration of the high period of the
clock signal. The data on the line must be changed
during the low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a START condi-
tion and terminated with a STOP condition. The
number of data bytes transferred between the
START and the STOP conditions is not limited, and
is determined by the master device. The informa-
SDA
SCL
START
CONDITION
MSB
1
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
2
6
7
8
9
ACK
Figure 3. 2-Wire Data Transfer Overview
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
1
2
3–7
8
9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERRED
STOP
CONDITION
OR REPEATED
START
CONDITION
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