DS1375 Datasheet, PDF (10/11 Pages) Dallas Semiconductor – 2-Wire Digital Input RTC with Alarm

2-Wire Digital Input RTC with Alarm
<SLAVE
<WORD
ADDRESS> ADDRESS (n)> <DATA (n)> <DATA (n + 1)> <DATA (n + X)>
S 1101000 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S — START
A — ACKNOWLEDGE
P — STOP
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D0H
Figure 4. Slave Receiver Mode (Write Mode)
tion is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device
must generate an extra clock pulse that is associat-
ed with this acknowledge bit.
A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable low during
the high period of the acknowledge-related clock
pulse. Setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
Figures 4 and 5 detail how data transfer is accom-
plished on the 2-wire bus. Depending upon the state of
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number
of data bytes. The slave returns an acknowledge bit
after each received byte.
Data transfer from a slave transmitter to a mas-
ter receiver. The master transmits the first byte (the
slave address). The slave then returns an acknowl-
edge bit. Next follows a number of data bytes
transmitted by the slave to the master. The master
returns an acknowledge bit after all received bytes,
other than the last byte. At the end of the last
received byte, a not acknowledge is returned.
The master device generates all the serial clock
pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a
repeated START condition. Since a repeated
START condition is also the beginning of the next
serial transfer, the bus is not released.
<SLAVE
ADDRESS>
<DATA (n)> <DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>
S 1101000 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S — START
A — ACKNOWLEDGE
P — STOP
A — NOT ACKNOWLEDGE
DATA TRANSFERRED
(X + 1 BYTES + ACKNOWLEDGE)
NOTE: LAST DATA BYTE IS FOLLOWED BY
A NOT ACKNOWLEDGE (A) SIGNAL
R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D0H
Figure 5. Slave Transmitter Mode (Read Mode)
The DS1375 can operate in the following two modes:
Slave Receiver Mode (Write Mode): Serial data
and clock are received through SDA and SCL. After
each byte is received, an acknowledge bit is trans-
mitted. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
Address recognition is performed by hardware
after reception of the slave address and direction
bit. The slave address byte is the first byte received
after the master generates the START condition.
The slave address byte contains the 7-bit DS1375
address, which is 1101000, followed by the direc-
tion bit (R/W), which is 0 for a write. After receiving
and decoding the slave address byte, the DS1375
outputs an acknowledge on SDA. After the DS1375
acknowledges the slave address + write bit, the
master transmits a word address to the DS1375.
This sets the register pointer on the DS1375, with
the DS1375 acknowledging the transfer. The mas-
ter can then transmit zero or more bytes of data,
with the DS1375 acknowledging each byte
received. The register pointer increments after
each data byte is transferred. The master gener-
ates a STOP condition to terminate the data write.
Slave Transmitter Mode (Read Mode): The first
byte is received and handled as in the slave receiv-
er mode. However, in this mode, the direction bit
indicates that the transfer direction is reversed. The
DS1375 transmits serial data on SDA while the seri-
al clock is input on SCL. START and STOP condi-
tions are recognized as the beginning and end of a
serial transfer. Address recognition is performed by
hardware after reception of the slave address and
direction bit. The slave address byte is the first byte
received after the master generates the START
condition. The slave address byte contains the 7-bit
DS1375 address, which is 1101000, followed by
the direction bit (R/W), which is 1 for a read. After
receiving and decoding the slave address byte, the
DS1375 outputs an acknowledge on SDA. The
DS1375 then begins to transmit data starting with
the register address pointed to by the register
pointer. If the register pointer is not written to before
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