DS1375 Datasheet, PDF (3/11 Pages) Dallas Semiconductor – 2-Wire Digital Input RTC with Alarm

2-Wire Digital Input RTC with Alarm
AC ELECTRICAL CHARACTERISTICS
(V_CC = V_CCMIN to V_CCMAX, T_A = -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 1)
PARAMETER
SCL Clock Frequency
Bus Free Time Between STOP
and START Conditions
Hold Time (Repeated) START
Condition (Note 8)
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time (Notes 9, 10)
Data Setup Time (Note 11)
Start Setup Time
Rise Time of Both SDA and SCL
Signals (Note 12)
Fall Time of Both SDA and SCL
Signals (Note 12)
Setup Time for STOP Condition
Capacitive Load for Each Bus
Line (Note 12)
Pulse Width of Spikes that Must
be Suppressed by the Input Filter
SYMBOL
f_SCL
t_BUF
t_HD:STA
t_LOW
t_HIGH
t_HD:DAT
t_SU:DAT
t_SU:STA
t_R
t_F
t_SU:STO
CONDITIONS
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
C_B
t_SP
Fast mode
MIN TYP
100
0
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0
0
100
250
0.6
4.7
20 + 0.1C_B
20 + 0.1C_B
0.6
4.7
MAX
400
100
UNITS
kHz
µs
µs
µs
µs
0.9
µs
0.9
ns
µs
300
ns
1000
300
ns
300
µs
400
pF
30
ns
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (see the V_IHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
The maximum t_HD:DAT is only met if the device does not stretch the low period (t_LOW) of the SCL signal.
A fast-mode device can be used in a standard-mode system, but the requirement t_SU:DAT ≥ 250ns must then be met.
This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t_{R MAX} + t_SU:DAT = 1000 + 250
= 1250ns before the SCL line is released.
C_B—total capacitance of one bus line in pF.
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