DS1375 Datasheet, PDF (8/11 Pages) Dallas Semiconductor – 2-Wire Digital Input RTC with Alarm

2-Wire Digital Input RTC with Alarm
Bit 7
ECLK
Bit 6
CLKSEL1
Bit 5
CLKSEL0
Bit 4
RS2
Control Register (0Eh)
Bit 7/Enable Clock (ECLK). When ECLK is set to logic
1, the CLK input pin is enabled to clock the internal
divider chain and advance the timekeeping registers.
When ECLK is set to logic 0, the divider chain is held in
reset, and the time is not allowed to advance. To syn-
chronize the DS1375 time to a reference, write the
ECLK bit to 0, write the time value, then write ECLK
back to 1. Doing so synchronizes the time value to with-
in one period of the CLK pin from the point in the inter-
face protocol where the ECLK bit is written. ECLK is set
to logic 1 when power is first applied.
Bits 6, 5/Clock Select Bits 1, 0 (CLKSEL1,
CLKSEL0). These bits determine how the CLK input
pin is divided down to get the 1Hz reference clock for
the timekeeping registers (Table 3). The CLKSEL0–1
bits are cleared to logic 0 when power is first applied.
Bits 4, 3/Rate Select (RS2 and RS1). These bits con-
trol the frequency of the square-wave output when the
square wave has been enabled and the CLKSEL0 and
CLKSEL1 bits are set to 0. Table 3 shows the square-
wave frequencies that can be selected with the RS bits.
These bits are set to logic 1 (8.192kHz) when power is
first applied. If either CLKSEL0 or CLKSEL1 are logic 1,
the 1Hz signal is output.
Bit 3
RS1
Bit 2
INTCN
Bit 1
A2IE
Bit 0
A1IE
Bit 2/Interrupt Control (INTCN). This bit controls the
SQW/INT signal. When the INTCN bit is set to logic 0, a
square wave is output on the SQW/INT pin. When the
INTCN bit is set to logic 1, a match between the time-
keeping registers and either of the alarm registers acti-
vates the SQW/INT (if the alarm is also enabled). The
corresponding alarm flag is always set, regardless of
the state of the INTCN bit. The INTCN bit is set to logic
0 when power is first applied.
Bit 1/Alarm 2 Interrupt Enable (A2IE). When set to
logic 1, this bit permits the alarm 2 flag (A2F) bit in the
status register to assert SQW/INT (when INTCN = 1).
When the A2IE bit is set to logic 0 or INTCN is set to
logic 0, the A2F bit does not initiate an interrupt signal.
The A2IE bit is disabled (logic 0) when power is first
applied.
Bit 0/Alarm 1 Interrupt Enable (A1IE). When set to
logic 1, this bit permits the alarm 1 flag (A1F) bit in the
status register to assert SQW/INT (when INTCN = 1).
When the A1IE bit is set to logic 0 or INTCN is set to
logic 0, the A1F bit does not initiate the SQW/INT sig-
nal. The A1IE bit is disabled (logic 0) when power is
first applied.
Table 3. CLK Input Frequency, Square-Wave Output Frequency
INTCN
1
0
0
0
0
0
0
0
CLKSEL1
X
0
0
0
0
0
1
1
CLKSEL0
X
0
0
0
0
1
0
1
INPUT FREQUENCY RS2 RS1
As selected
32,768Hz
32,768Hz
32,768Hz
32,768Hz
8192Hz
60Hz
50Hz
X
X
0
0
0
1
1
0
1
1
X
X
X
X
X
X
8 _____________________________________________________________________
SQUARE-WAVE OUTPUT
FREQUENCY
N/A (Interrupt)
1Hz
1.024kHz
4.096kHz
8.192kHz
1Hz
1Hz
1Hz