DS80C410 Datasheet, PDF (6/102 Pages) Dallas Semiconductor – Network Microcontrollers with Ethernet and CAN

DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
PARAMETER
SYMBOL
Data Float After RD (P3.7 or
PSEN) High
tRHDZ
ALE Low to Valid Data In
tLLDV
Port 0 Address to Valid Data
In
tAVDV0
Port 2, 4, 6 Address, Port 4
CE, or Port 5 PCE to Valid
Data In
tAVDV2
ALE Low to (RD or PSEN) or
WR Low
tLLWL
Port 0 Address to (RD or
PSEN) or WR Low
Port 2, 4 Address, Port 4 CE,
Port 5 PCE, to (RD or PSEN)
or WR Low
Data Valid to WR Transition
tAVWL0
tAVWL2
tQVWX
Data Hold After WR High
tWHQX
RD Low to Address Float
(RD or PSEN) or WR High to
ALE
(RD or PSEN) or WR High to
Port 4 CE or Port 5 PCE
High
tRLAZ
tWHLH
tWHLH2
MIN
MAX
tCLCH - 3
tCLCL - 3
5tCLCL - 3
tCLCL – 6.5
2tCLCL – 6.5
10tCLCL – 7
tCLCL + tCLCH - 7
2tCLCL + tCLCH - 7
10tCLCL + tCLCH - 7
0
tCLCL - 5
2CLCL - 8
6tCLCL - 8
-2.5
tCLCL – 2.5
5tCLCL – 2.5
tCHCL -5
tCLCL + tCHCL - 5
5tCLCL + tCHCL - 5
tCLCL - 5
2tCLCL - 5
6tCLCL - 5
2tCLCL + tCLCH - 19
(4 x CST + 1) tCLCL - 19
(4 x CST + 5) tCLCL - 19
3tCLCL - 19
(4 x CST + 2)tCLCL - 19
(4 x CST + 10)tCLCL - 20
3tCLCL + tCLCH - 22
(4 x CST + 2)tCLCL + tCLCH -
22
(4 x CST + 10)tCLCL + tCLCH -
22
tCLCH + 6
tCLCL + 6
5tCLCL + 6
(Note 2)
6
tCLCL + 6
5tCLCL + 6
tCHCL + 13
tCLCL + tCHCL + 13
5tCLCL + tCHCL + 13
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STRETCH VALUES
CST (MD2:0)
CST = 0
1£ CST £ 3
4 £ CST £ 7
CST = 0
1£ CST £ 3
4 £ CST £ 7
CST = 0
1£ CST £ 3
4 £ CST £ 7
CST = 0
1£ CST £ 3
4 £ CST £ 7
CST = 0
1 £ CST £ 3
4 £ CST £ 7
CST = 0
1 £ CST £ 3
4 £ CST £ 7
CST = 0
1 £ CST £ 3
4 £ CST £ 7
CST = 0
1 £ CST £ 3
4 £ CST £ 7
0£ CST £ 7
CST = 0
1 £ CST £ 3
4 £ CST £ 7
CST = 0
1 £ CST £ 3
4 £ CST £ 7
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production
tested, but are guaranteed by design.
For a MOVX read operation, on the falling edge of ALE, Port 0 is held by a weak latch until overdriven by external memory.
All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. tCLCL , tCLCH , tCHCL are time
periods associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7
(PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
References to the XTAL, XTAL1 or CLK signal in the timing diagrams are to assist in determining the relative occurrence of events,
not for determining absolute signal timing with respect to the external clock.
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