DS80C410 Datasheet, PDF (44/102 Pages) Dallas Semiconductor – Network Microcontrollers with Ethernet and CAN

DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
ADDRESSING MODES
Three different addressing modes are supported, as selected by the AM1, AM0 bits in the address control (ACON;
9Dh) SFR.
AM1:0
00b
01b
1xb
ADDRESS MODE
16-bit (default when internal ROM disabled)
24-bit paged
24-bit contiguous (default if internal ROM enabled)
16-Bit Address Mode
The 16-bit address mode accesses memory in a similar manner as a traditional 8051. It is op-code compatible with
the 8051 microprocessor and identical to the byte and cycle count of the Dallas Semiconductor high-speed
microcontroller family. A device operating in this mode can access up to 64kB of program and data memory. The
DS80C410 defaults to this mode following any reset.
24-Bit Paged Address Mode
The 24-bit paged address mode retains binary-code compatibility with the 8051 instruction set, but adds one
machine cycle to the ACALL, LCALL, RET, and RETI instructions with respect to the Dallas Semiconductor high-
speed microcontroller family timing. This is transparent to standard 8051 compilers. Interrupt latency is also
increased by one machine cycle. In this mode, interrupt vectors are fetched from 0000xxh.
24-Bit Contiguous Address Mode
The 24-bit contiguous addressing mode uses a full 24-bit program counter, and all modified branching instructions
automatically save and restore the entire program counter. The 24-bit branching instructions such as ACALL,
AJMP, LCALL, LJMP, MOV DPTR, RET, and RETI instructions require an assembler, compiler, and linker that
specifically supports these features. The INC DPTR is lengthened by one cycle but remains byte-count compatible
with the standard 8051 instruction set.
Visit www.maxim-ic.com/microcontrollers for a list of tools that support the DS80C410.
Extended Address Generation
FUNCTION
ADDRESS BITS 23–16
ADDRESS BITS 15–8
ADDRESS BITS 7–0
MOVX Instructions Using DPTRn
DPXn
DPHn
DPLn
MOVX Instructions Using @Ri
Addressing Program Memory In 24-Bit
Paged Mode
10-Bit Stack Pointer Mode
MXAX;EAh
AP;9Ch
—
P2;A0h
—
ESP;9Bh
Ri
—
SP;81h
External Program Memory Addressing
Since the DS80C410 is not bound to the 8051’s traditional 16-bit address mode, on-chip hardware enhancements
were made to accommodate the larger memory interfaces associated with 24-bit addressing. The DS80C410
provides SFR bits to configure certain port pins as upper address lines and chip enables. The Port 4 control
register (P4CNT; 92h) and Port 6 control register (P6CNT; B2h) control the number of chip enables that are used
and the maximum amount of program memory that can be accessed per chip enable. Tables 3 and 4 illustrate
which port pins are converted to address lines or chip enables as a result of the P4CNT and P6CNT bit settings.
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