DS80C410 Datasheet, PDF (34/102 Pages) Dallas Semiconductor – Network Microcontrollers with Ethernet and CAN

DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
PIN
NAME
FUNCTION
MII Management Input/Output. The MII management I/O is the data pin for serial communication with the
19
MDIO
external Ethernet PHY controller. In a read cycle, data is driven by the PHY to the MAC synchronously with
respect to the MDC clock. In a write cycle, data from the MAC is output to the external PHY synchronously with
respect to the MDC clock.
1-Wire Data, I/O. The 1-Wire data pin is an open-drain, bidirectional data bus for the 1-Wire Bus Master.
99
OW
External 1-Wire slave devices are connected to this pin. This pin must be pulled high by an external resistor,
normally 2.2kW.
Strong Pullup Enable, Output. This 1-Wire pin is an open-drain active-low output used to enable an external
strong pullup for the 1-Wire bus. This pin must be pulled high by an external resistor, normally 10kW. This
100
OWSTP functionality helps recovery times when the 1-Wire bus is operated in overdrive and long-line standard
communication modes. It can optionally be enabled while the bus master is in the idle state for slave devices
requiring sustained high-current operation.
FEATURES (continued)
§ Full-Function CAN 2.0B Controller
15 Message Centers
Supports Standard (11-Bit) and Extended (29-Bit)
Identifiers and Global Masks
Media Byte Filtering to Support DeviceNet^™, SDS,
and Higher Layer CAN Protocols
Auto-Baud Mode and SIESTA Low-Power Mode
§ Integrated Primary System Logic
16 Total Interrupt Sources with Six External
Four 16-Bit Timer/Counters
2x/4x Clock Multiplier Reduces Electromagnetic
Interference (EMI)
Programmable Watchdog Timer
Oscillator-Fail Detection
Programmable IrDA Clock
§ Advanced Power Management
Energy Saving 1.8V Core
3.3V I/O Operation, 5V Tolerant
Power-Management, Idle, and Stop Mode
Operations with Switchback Feature
Ethernet and CAN Shutdown Control for Power
Conservation
Early Warning Power-Fail Interrupt
Power-Fail Reset
§ Enhanced Memory Architecture
Selectable 8/10-Bit Stack Pointer for High-Level
Language Support
64kBytes Additional On-Chip SRAM Usable as
Program/Data Memory
16-Bit/24-Bit Paged/24-Bit Contiguous Modes
Selectable Multiplexed/Nonmultiplexed External
Memory Interface
Merged Program/Data Memory Space Allows In-
System Programming
Defaults to True 8051-Memory Compatibility
DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc.
34 of 102