DS80C410 Datasheet, PDF (31/102 Pages) Dallas Semiconductor – Network Microcontrollers with Ethernet and CAN

DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
PIN DESCRIPTION
PIN
70
12, 36, 62,
87
13, 39, 63,
88
68
67
69
40
97
98
37
38
86
85
84
83
82
81
80
79
89
90
91
92
93
94
95
96
66
65
64
61
60
59
NAME
VCC1
VCC3
VSS
ALE
PSEN
EA
MUX
RST
RSTOL
XTAL2
XTAL1
AD0/D0
AD1/D1
AD2/D2
AD3/D3
AD4/D4
AD5/D5
AD6/D6
AD7/D7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
A8
A9
A10
A11
A12
A13
+1.8V Core Supply Voltage
+3.3V I/O Supply Voltage
FUNCTION
Digital Circuit Ground
Address Latch Enable, Output. When the MUX pin is low, this pin outputs a clock to latch the external address
LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of
an external transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles.
When the MUX pin is high, the pin toggles continuously if the ALEOFF bit is cleared. ALE is forced high when
the device is in a reset condition or if the ALEOFF bit is set while the MUX pin is high.
Program Store Enable, Output. This signal is the chip enable for external program or merged program/data
memory. PSEN provides an active-low pulse and is driven high when external memory is not being accessed.
External Access Enable, Input. Connect to GND to use external program memory. Connect to VCC to use
internal ROM.
Multiplex/Demultiplex Select, Input. This pin selects if the address/data bus operates in multiplexed (MUX =
0) or demultiplexed (MUX = 1) mode. The MUX pin is sampled only on a power-on reset.
Reset, Input. The RST input pin contains a Schmitt voltage input to recognize external active-high reset inputs.
The pin also employs an internal pulldown resistor to allow for a combination of wired-OR external-reset
sources. An RC circuit is not required for power-up, as the device provides this function internally.
Reset Output Low, Output. This active-low signal is asserted when the microcontroller has entered reset
through the RST pin; during crystal warm-up period following power-on or stop mode; during a watchdog timer
reset; during an oscillator failure (if OFDE = 1); whenever VCC1 £ VRST1 or VCC3 £ VRST3.
XTAL1, XTAL2. Crystal oscillator pins support fundamental mode, parallel resonant, AT cut crystals. XTAL1 is
the input if an external clock source is used in place of a crystal. XTAL2 is the output of the crystal amplifier.
AD0–7 (Port 0), I/O. When the MUX pin is connected low, Port 0 is the multiplexed address/data bus. While
ALE is high, the LSB of a memory address is presented. While ALE falls, the port transitions to a bidirectional
data bus. When the MUX pin is connected high, Port 0 functions as the bidirectional data bus. Port 0 cannot be
modified by software. The reset condition of Port 0 pins is high. No pullup resistors are needed.
Port
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Alternate Function
AD0/D0 (Address)/Data 0
AD1/D1 (Address)/Data 1
AD2/D2 (Address)/Data 2
AD3/D3 (Address)/Data 3
AD4/D4 (Address)/Data 4
AD5/D5 (Address)/Data 5
AD6/D6 (Address)/Data 6
AD7/D7 (Address)/Data 7
Port 1, I/O. Port 1 can function as either an 8-bit, bidirectional I/O port or as an alternate interface for internal
resources. The reset condition of Port 1 is all bits at logic 1 through a weak pullup. The logic 1 state also serves
as an input mode, since external circuits writing to the port can override the weak pullup. When software clears
any port pin to 0, a strong pulldown is activated that remains on until either a 1 is written to the port pin or a
reset occurs. Writing a 1 after the port has been at 0 activates a strong transition driver, followed by a weaker
sustaining pullup. Once the momentary strong driver turns off, the port once again becomes the output (and
input) high state.
Port
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Alternate Function
T2 External I/O for Timer/Counter 2
T2EX Timer/Counter 2 Capture/Reload Trigger
RXD1 Serial Port 1 Receive
TXD1 Serial Port 1 Transmit
INT2 External Interrupt 2 (Positive Edge Detect)
INT3 External Interrupt 3 (Negative Edge Detect)
INT4 External Interrupt 4 (Positive Edge Detect)
INT5 External Interrupt 5 (Negative Edge Detect)
A15–A8 (Port 2), Output. Port 2 serves as the MSB for external addressing. The port automatically asserts the
address MSB during external ROM and RAM access. Although the Port 2 SFR exists, the SFR value never
appears on the pins (due to memory access). Therefore, accessing the Port 2 SFR is only useful for MOVX A,
@Ri or MOVX @Ri, A instructions, which use the Port 2 SFR as the external address MSB.
Port
P2.0
P2.1
P2.2
P2.3
Alternate Function
A8 Program/Data Memory Address 8
A9 Program/Data Memory Address 9
A10 Program/Data Memory Address 10
A11 Program/Data Memory Address 11
31 of 102