DS80C410 Datasheet, PDF (56/102 Pages) Dallas Semiconductor – Network Microcontrollers with Ethernet and CAN

DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
Each CSR register is documented as follows:
CSR Register:
Register Address:
MAC Control
00h
Bit Names:
31
RA
BLE
—
HBD
PS
—
—
—
24
23
DRO
OM[1:0]
F
PM
PR
IF
PB 16
15
HO
—
HP
LCC
DBF
DRTY
—
ASTP 8
7
BLOMT[1:0]
DC
—
TE
RE
—
—
0
Reset State:
31
0
0
0
0
0
0
0
0
24
23
0
0
0
0
0
1
0
0
16
15
0
0
0
0
0
0
0
0
8
7
0
0
0
0
0
0
0
0
0
RA, Receive All. This bit overrides the flush-filter failed-packet function if that function has been enabled
(EBS.7 = 1).
0 = default frame handling (default)
1 = all error-free frames are received with packet filter bit set (= 1) in the receive status word
BLE, Big/Little Endian Mode
0 = data buffers are operated in little Endian mode (default)
1 = data buffers are operated in big Endian mode
HBD, Heart-Beat Disable. This bit is only useful in ENDEC mode and has no affect on MII mode operation.
0 = heart-beat signal quality-generator function enabled (default)
1 = heart-beat signal quality-generator function is disabled
PS, Port Select
0 = MII mode (default)
1 = ENDEC mode
DRO, Disable Receive Own. This bit should always be cleared to a logic 0 for full-duplex operation and any
loopback operating modes other than “normal mode.”
0 = MAC receives all packets given by the PHY (default)
1 = MAC disables reception of frames during frame transmission (TX_EN = 1)
OM[1:0], Loopback Operating Mode
00 = normal mode, no loopback (default)
01 = internal loopback through MII
10 = external loopback through PHY
11 = reserved
F, Full-Duplex Mode
0 = half-duplex mode (default)
1 = full-duplex mode
PM, Pass All Multicast
0 = multicast frames filtered according to current multicast filter mode (default)
1 = pass all multicast frames; filter-fail bit is reset (= 0) for all multicast frames received
PR, Promiscuous Mode
0 = promiscuous mode disabled
1 = promiscuous mode enabled (default)
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