DS80C320 Datasheet, PDF (4/42 Pages) Dallas Semiconductor – High-Speed/Low-Power Micro

PIN DESCRIPTION Table 1
DIP PLCC TQFP SIGNAL NAME
40
44
38
20 22, 23 16, 17
V_CC
GND
9
10
4
RST
18
20
14
19
21
15
29
32
26
XTAL2
XTAL1
PSEN
30
33
27
ALE
39
43
37
38
42
36
37
41
35
36
40
34
35
39
33
34
38
32
33
37
31
32
36
30
1-8 2-9 40-44
1-3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
P1.0-P1.7
1
2
40
2
3
41
3
4
42
4
5
43
5
6
44
6
7
1
7
8
2
8
9
3
DS80C320/DS80C323
DESCRIPTION
V_CC - +5V. (+3V DS80C323)
GND - Digital circuit ground.
RST - Input. The RST input pin contains a Schmitt voltage input to
recognize external active high Reset inputs. The pin also employs an
internal pulldown resistor to allow for a combination of wired OR
external Reset sources. An RC is not required for power-up, as the
device provides this function internally.
XTAL1, XTAL2 - The crystal oscillator pins XTAL1 and XTAL2
provide support for parallel resonant, AT cut crystals. XTAL1 acts
also as an input in the event that an external clock source is used in
place of a crystal. XTAL2 serves as the output of the crystal
amplifier.
PSEN - Output. The Program Store Enable output. This signal is
commonly connected to external ROM memory as a chip enable.
PSEN will provide an active low pulse width of 2.25 XTAL1 cycles
with a period of four XTAL1 cycles. PSEN is driven high when data
memory (RAM) is being accessed through the bus and during a reset
condition.
ALE – Output. The Address Latch Enable output functions as a
clock to latch the external address LSB from the multiplexed
address/data bus. This signal is commonly connected to the latch
enable of an external 373 family transparent latch. ALE has a pulse
width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE
is forced high when the device is in a Reset condition.
AD0-7 (Port 0) - I/O. Port 0 is the multiplexed address/data bus.
During the time when ALE is high, the LSB of a memory address is
presented. When ALE falls, the port transitions to a bi-directional
data bus. This bus is used to read external ROM and read/write
external RAM memory or peripherals. The Port 0 has no true port
latch and can not be written directly by software. The reset condition
of Port 0 is high. No pullup resistors are needed.
Port 1 - I/O. Port 1 functions as both an 8-bit bi-directional I/O port
and an alternate functional interface for Timer 2 I/O, new External
Interrupts, and new Serial Port 1. The reset condition of Port 1 is with
all bits at a logic 1. In this state, a weak pullup holds the port high.
This condition also serves as an input mode, since any external
circuit that writes to the port will overcome the weak pullup. When
software writes a 0 to any port pin, the device will activate a strong
pulldown that remains on until either a 1 is written or a reset occurs.
Writing a 1 after the port has been at 0 will cause a strong transition
driver to turn on, followed by a weaker sustaining pullup. Once the
momentary strong driver turns off, the port once again becomes the
output high (and input) state. The alternate modes of Port 1 are
outlined as follows:
Port
Alternate Function
P1.0
T2
External I/O for Timer/Counter 2
P1.1
T2EX
Timer/Counter 2 Capture/Reload Trigger
P1.2
RXD1
Serial Port 1 Input
P1.3
TXD1
Serial Port 1 Output
P1.4
INT2
External Interrupt 2 (Positive Edge Detect)
P1.5
INT3
P1.6
INT4
External Interrupt 3 (Negative Edge Detect)
External Interrupt 4 (Positive Edge Detect)
P1.7
INT5
External Interrupt 5 (Negative Edge Detect)
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