DS80C320 Datasheet, PDF (10/42 Pages) Dallas Semiconductor – High-Speed/Low-Power Micro

SPEED ADVANTAGE SUMMARY
#Opcodes
Speed Improvement
159
3.0 x
51
1.5 x
43
2.0 x
2
2.4 x
255
Average: 2.5
DS80C320/DS80C323
MEMORY ACCESS
The DS80C320/DS80C323 contains no on-chip ROM and 256 bytes of scratchpad RAM. Off-chip
memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. A typical
memory connection is shown in Figure 3. Timing diagrams are provided in the Electrical Specifications.
Program memory (ROM) is accessed at a fixed rate determined by the crystal frequency and the actual
instructions. As ment ioned above, an instruction cycle requires 4 clocks. Data memory (RAM) is
accessed according to a variable speed MOVX instruction as described below.
TYPICAL MEMORY CONNECTION Figure 3
STRETCH MEMORY CYCLE
The DS80C320/DS80C323 allows the application software to adjust the speed of data memory access.
The microcontroller is capable of performing the MOVX in as little as two instruction cycles. However,
this value can be stretched as needed so that both fast memory and slow memory or peripherals can be
accessed with no glue logic. Even in high-speed systems, it may not be necessary or desirable to perform
data memory access at full speed. In addition, there are a variety of memory mapped peripherals such as
LCD displays or UARTs that are not fast.
The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below.
This allows the user to select a stretch value between 0 and 7. A Stretch of 0 will result in a two-machine
cycle MOVX. A Stretch of 7 will result in a MOVX of nine machine cycles. Software can dynamically
change this value depending on the particular memory or peripheral.
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