DS80C320 Datasheet, PDF (15/42 Pages) Dallas Semiconductor – High-Speed/Low-Power Micro

DS80C320/DS80C323
As shown above, the watchdog timer uses the crystal frequency as a time base. A user selects one of four
counter values to determine the timeout. These clock counter lengths are 2¹⁷ = 131,072 clocks; 2²⁰=
1,048,576; 2²³= 8,388,608 clocks; or 2²⁶= 67,108,864 clocks. The times shown in Table 4 are with a 25
MHz crystal frequency. Note that once the counter chain has reached a conclusion, the optional interrupt
is generated. Regardless of whether the user enables this interrupt, there are then 512 clocks left until a
reset occurs. There are 5 control bits in special function registers that affect the Watchdog Timer and two
status flags that report to the user. The Reset Watchdog Timer bit (WDCON.0) should be asserted prior to
modifying the Watchdog Timer Mode Select bits (WD1, WD0) to avoid corruption of the watchdog
count.
WDIF (WDCON.3) is the interrupt flag that is set when there are 512 clocks remaining until a reset
occurs. WTRF (WDCON.2) is the flag that is set when a Watchdog reset has occurred. This allows the
application software to determine the source of a reset.
Setting the EWT (WDCON.1) bit enables the Watchdog Timer. The bit is protected by Timed Access
discussed below. Setting the RWT (WDCON.0) bit restarts the Watchdog Timer for another full interval.
Application software must set this bit prior to the timeout. As mentioned previously, WD1 and 0
(CKCON .7 and 6) select the timeout. Finally, the Watchdog Interrupt is enabled using EWDI (EIE.4).
INTERRUPTS
The DS80C320/DS80C323 provides 13 sources of interrupt with three priority levels. The Power-fail
Interrupt (PFI), if enabled, always has the highest priority. There are two remaining user selectable
priorities: high and low. If two interrupts that have the same priority occur simultaneously, the natural
precedence given belo w determines which is a acted upon. Except for the PFI, all interrupts that are new
to the 8051 family have a lower natural priority than the originals.
INTERRUPT PRIORITY Table 5
NAME DESCRIPTION
PFI
Power- fail Intterupt
INT0
TF0
External Interrupt 0
Timer 0
INT1
TF1
External Interrupt 1
Timer 1
SCON0 TI0 or RI0 from serial port 0
TF2
Timer 2
SCON1 TI1 or RI1 from serial port 1
INT2 External Interrupt 2
INT3
INT4
External Interrupt 3
External Interrupt 4
INT5
WDTI
External Interrupt 5
Watchdog Timeout Interrupt
VECTOR
33h j
03h
0Bh
13h
1Bh
23h
2Bh
3Bh
43h
4Bh
53h
5Bh
63h
NATURAL PRIORITY
1
2
3
4
5
6
7
8
9
10
11
12
13
OLD/NEW
NEW
OLD
OLD
OLD
OLD
OLD
OLD
NEW
NEW
NEW
NEW
NEW
NEW
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