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BCM43362KUBGT Datasheet, PDF (78/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO | |||
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BCM43362 Data Sheet
SDIO High-Speed Mode Timing
SDIO High-Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 26 and Table 25.
Figure 26: SDIO Bus Timing (High-Speed Mode)
50% VDD
SDIO_CLK
fPP
tWL
tWH
Input
tTHL
tISU
tTLH
tIH
Output
tODLY
tOH
Table 25: SDIO Bus Timing a Parameters (High-Speed Mode)
Parameter
Symbol Minimum Typical
SDIO CLK (all values are referred to minimum VIH and maximum VILb)
Frequency â Data Transfer Mode
fPP
0
â
Frequency â Identification Mode
fOD
0
â
Clock low time
tWL
7
â
Clock high time
tWH
7
â
Clock rise time
tTLH
â
â
Clock fall time
tTHL
â
â
Inputs: CMD, DAT (referenced to CLK)
Input setup Time
tISU
6
â
Input hold Time
tIH
2
â
Outputs: CMD, DAT (referenced to CLK)
Output delay time â Data Transfer Mode
tODLY
â
â
Output hold time
tOH
2.5
â
Total system capacitance (each line)
CL
â
â
a. Timing is based on CL ï£ 40pF load on CMD and Data.
b. min(Vih) = 0.7 Ã VDDIO and max(Vil) = 0.2 Ã VDDIO.
Maximum Unit
50
MHz
400
kHz
â
ns
â
ns
3
ns
3
ns
â
ns
â
ns
14
ns
â
ns
40
pF
Broadcom®
February 13, 2015 ⢠43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 77
BROADCOM CONFIDENTIAL
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