BCM43362KUBGT Datasheet, PDF (40/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
Figure 18: WLAN PHY Block Diagram
PHY Description
AFE
and
Radio
Filters
and
Radio
Comp
Radio
Control
Block
Filters and
Radio Comp
Frequency
and Timing
Synch
Carrier Sense,
AGC, and Rx
FSM
Tx FSM
PA Comp
Buffers
CCK/DSSS
Demodulate
OFDM
Demodulate
Viterbi
Decoder
FFT/IFFT
Modulation
and Coding
Modulate/
Spread
Descramble
and
Deframe
MAC
Interface
Frame and
Scramble
COEX
The PHY is capable of fully calibrating the RF front-end to extract the highest performance. On power-up, the
PHY performs a full calibration suite to correct for IQ mismatch and local oscillator leakage. The PHY also
performs periodic calibration to compensate for any temperature related drift, thus maintaining high-
performance over time. A closed loop transmit control algorithm maintains the output power to required level
with capability control Tx power on a per packet basis.
One of the key feature of the PHY is two space-time stream receive capability. The STBC scheme can obtain
diversity gains by using multiple transmit antennas in AP (Access Point) in a fading channel environment,
without increasing the complexity at the STA. Details of the STBC receive are shown in the block diagram in
Figure 19 on page 40.
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 39
BROADCOM CONFIDENTIAL