BCM43362KUBGT Datasheet, PDF (33/84 Pages) Cypress Semiconductor – Single-Chip IEEE 802.11™ b/g/n MAC/Baseband/Radio + SDIO

BCM43362 Data Sheet
Generic SPI Mode
Figure 15: WLAN Boot-Up Sequence
32.768 kHz
LPO Sleep
Clock
VBAT
Ramp time from 0V to 4.3V > 40 µs
0.6V
VDDIO
WL_RST_N/
EXT_SMPS_REQ
VDDC
(from internal PMU)
> 2 Sleep Clock cycles
< 1.5 ms
< 3 ms
Internal POR
< 50 ms
After a fixed delay following internal POR going high,
the device responds to host F0 (address 0x14) reads.
Device requests for reference clock
SPI Host Interaction:
8 ¹ ms
After 8 ms¹ the reference clock
is assumed to be up. Access to
PLL registers is possible.
Host polls F0 (address 0x14) until it reads
a predefined pattern.
Host sets wake-up-wlan bit
and waits 8 ms¹, the
maximum time for
reference clock availability.
After 8 ¹ ms, the host
programs the PLL registers to
set the crystal frequency
WL_IRQ
Chip-active interrupt is asserted after the PLL locks
Host downloads
code.
1 _{This wait time is programmable in sleep clock increments from 1 to 255 (30 us to 8 ms)}
Broadcom_®
February 13, 2015 • 43362-DS106-R
IEEE 802.11 b/g/n MAC/Baseband/Radio + SDIO
Page 32
BROADCOM CONFIDENTIAL