S25FS064S Datasheet, PDF (74/147 Pages) Cypress Semiconductor – 64 Mbit (8 Mbyte), 1.8-V FS-S Flash

PRELIMINARY
S25FS064S
 All instruction, address, mode, and data information is transferred in byte granularity. Addresses are shifted into the device with
the most significant byte first. All data is transferred with the lowest address byte sent first. Following bytes of data are sent in
lowest to highest byte address order i.e. the byte address increments.
 All attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. The
embedded operation will continue to execute without any affect. A very limited set of commands are accepted during an
embedded operation. These are discussed in the individual command descriptions. While a program, erase, or write operation is
in progress, it is recommended to check that the Write-In Progress (WIP) bit is 0 before issuing most commands to the device, to
ensure the new command can be accepted.
 Depending on the command, the time for execution varies. A command to read status information from an executing command is
available to determine when the command completes execution and whether the command was successful.
 Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces of the host
system and the memory device generally handle the details of signal relationships and timing. For this reason, signal relationships
and timing are not covered in detail within this software interface focused section of the document. Instead, the focus is on the
logical sequence of bits transferred in each command rather than the signal timing and relationships. Following are some general
signal relationship descriptions to keep in mind. For additional information on the bit level format and signal timing relationships of
commands, see Section 4.2, Command Protocol on page 13.
– The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI/IO0) for single bit wide transfers.
The memory drives Serial Output (SO/IO1) for single bit read transfers. The host and memory alternately drive the IO0-IO3
signals during Dual and Quad transfers.
– All commands begin with the host selecting the memory by driving CS# low before the first rising edge of SCK. CS# is kept
low throughout a command and when CS# is returned high the command ends. Generally, CS# remains low for eight bit
transfer multiples to transfer byte granularity information. Some commands will not be accepted if CS# is returned high not at
an 8 bit boundary.
11.1 Command Set Summary
11.1.1 Extended Addressing
1. Instructions that always require a 4-Byte address, used to access up to 32 Gb of memory:
Command Name
4READ
4FAST_READ
4DOR
4QOR
4DIOR
4QIOR
4DDRQIOR
4PP
4QPP
4P4E
4SE
4ECCRD
4DYBRD
4DYBWR
4PPBRD
4PPBP
Function
Read
Read Fast
Dual Output Read
Quad Output Read
Dual I/O Read
Quad I/O Read
DDR Quad I/O Read
Page Program
Quad Page Program
Parameter 4 KB Erase
Erase 64 KB
ECC Status Read
DYB Read
DYBWR
PPB Read
PPB Program
Instruction (Hex)
13
0C
3C
6C
BC
EC
EE
12
34
21
DC
18
E0
E1
E2
E3
Document Number: 002-03631 Rev. *C
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