S25FS064S Datasheet, PDF (48/147 Pages) Cypress Semiconductor – 64 Mbit (8 Mbyte), 1.8-V FS-S Flash

PRELIMINARY
S25FS064S
Table 9.8 OTP Address Map
Region
Region 0
Region 1
Region 2
...
Region 31
Byte Address Range (Hex)
000
...
00F
010 to 013
014 to 01F
020 to 03F
040 to 05F
...
3E0 to 3FF
Contents
Least Significant Byte of Cypress
Programmed Random Number
...
Most Significant Byte of Cypress
Programmed Random Number
Region Locking Bits
Byte 10 [bit 0] locks region 0 from
programming when = 0
...
Byte 13 [bit 7] locks region 31from
programming when = 0
Reserved for Future Use (RFU)
Available for User Programming
Available for User Programming
Available for User Programming
Available for User Programming
Initial Delivery State (Hex)
Cypress Programmed Random Number
All Bytes = FF
All Bytes = FF
All Bytes = FF
All Bytes = FF
All Bytes = FF
All Bytes = FF
9.6 Registers
Registers are small groups of memory cells used to configure how the FS-S Family memory device operates or to report the status
of device operations. The registers are accessed by specific commands. The commands (and hexadecimal instruction codes) used
for each register are noted in each register description.
In legacy SPI memory devices the individual register bits could be a mixture of volatile, non-volatile, or One Time Programmable
(OTP) bits within the same register. In some configuration options the type of a register bit could change e.g. from non-volatile to
volatile.
The FS-S Family uses separate non-volatile or volatile memory cell groups (areas) to implement the different register bit types.
However, the legacy registers and commands continue to appear and behave as they always have for legacy software compatibility.
There is a non-volatile and a volatile version of each legacy register when that legacy register has volatile bits or when the command
to read the legacy register has zero read latency. When such a register is read the volatile version of the register is delivered. During
Power-On Reset (POR), hardware reset, or software reset, the non-volatile version of a register is copied to the volatile version to
provide the default state of the volatile register. When non-volatile register bits are written the non-volatile version of the register is
erased and programmed with the new bit values and the volatile version of the register is updated with the new contents of the non-
volatile version. When OTP bits are programmed the non-volatile version of the register is programmed and the appropriate bits are
updated in the volatile version of the register. When volatile register bits are written, only the volatile version of the register has the
appropriate bits updated.
The type for each bit is noted in each register description. The default state shown for each bit refers to the state after power-on
reset, hardware reset, or software reset if the bit is volatile. If the bit is non-volatile or OTP, the default state is the value of the bit
when the device is shipped from Cypress. Non-volatile bits have the same cycling (erase and program) endurance as the main Flash
array.
Table 9.9 Register Descriptions
Register
Status Register-1
Status Register-2
Configuration Register-1
Configuration Register-2
Document Number: 002-03631 Rev. *C
Type
Non-volatile
Volatile
Volatile
Non-volatile/OTP
Volatile
Non-volatile/OTP
Volatile
Bits
Abbreviation
7:0
SR1NV[7:0]
7:0
SR1V[7:0]
7:0
SR2V[7:0]
7:0
CR1NV[7:0]
7:0
CR1V[7:0]
7:0
CR2NV[7:0]
7:0
CR2V[7:0]
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