S25FS064S Datasheet, PDF (32/147 Pages) Cypress Semiconductor – 64 Mbit (8 Mbyte), 1.8-V FS-S Flash

PRELIMINARY
S25FS064S
6.4 SDR AC Characteristics
Table 6.4 SDR AC Characteristics
Symbol
F_{SCK, R}
F_{SCK, C}
P_SCK
t_WH, t_CH
t_WL, t_CL
t_CRT, t_CLCH
t_CFT, t_CHCL
t_CS
t_CSS
t_CSH
t_SU
t_HD
Parameter
SCK Clock Frequency for READ and 4READ instructions
SCK Clock Frequency for the following dual and quad commands: DOR, 4DOR, DIOR,
4DIOR, QOR, 4QOR, QIOR, 4QIOR
SCK Clock Period
Clock High Time
Clock Low Time
Clock Rise Time (slew rate)
Clock Fall Time (slew rate)
CS# High Time (Read Instructions)
CS# High Time (Read Instructions when Reset feature and Quad mode are both
enabled)
CS# High Time (Program/Erase Instructions)
CS# Active Setup Time (relative to SCK)
CS# Active Hold Time (relative to SCK)
Data in Setup Time
Data in Hold Time
Min
DC
DC
1/ F_SCK
50% P_SCK -5%
50% P_SCK -5%
0.1
0.1
10
20 (5)
50
2
3
2
3
t_V
Clock Low to Output Valid
t_HO
Output Hold Time
1
t_DIS
Output Disable Time (4)
Output Disable Time (when Reset feature and Quad mode are both enabled)
t_WPS
WP# Setup Time (1)
20
t_WPH
WP# Hold Time (1)
100
t_DPD
CS# High to Power-down Mode
t_RES
CS# High to Standby Mode without Electronic Signature
Read
Notes:
1. Only applicable as a constraint for WRR or WRAR instruction when SRWD is set to a 1
2. Full V_DD range and CL=30 pF
3. Full V_DD range and CL=15 pF
4. Output HI-Z is defined as the point where data is no longer driven.
5. t_CS and t_DIS require additional time when the Reset feature and Quad mode are enabled (CR2V[5]=1 and CR1V[1]=1).
6. SOIC package
Max
50
133
50% P_SCK +5%
50% P_SCK +5%
8 (2)
6 (3)
6.5 (3)(6)
8
20 (5)
3
30
Unit
MHz
MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
Document Number: 002-03631 Rev. *C
Page 32 of 147