S25FS064S Datasheet, PDF (73/147 Pages) Cypress Semiconductor – 64 Mbit (8 Mbyte), 1.8-V FS-S Flash

PRELIMINARY
S25FS064S
11. Commands
All communication between the host system and FS-S Family memory devices is in the form of units called commands.
All commands begin with an instruction that selects the type of information transfer or device operation to be performed. Commands
may also have an address, instruction modifier, latency period, data transfer to the memory, or data transfer from the memory. All
instruction, address, and data information is transferred sequentially between the host system and memory device.
Command protocols are also classified by a numerical nomenclature using three numbers to reference the transfer width of three
command phases:
 instruction;
 address and instruction modifier (mode);
 data.
Single bit wide commands start with an instruction and may provide an address or data, all sent only on the SI/IO0 signal. Data may
be sent back to the host serially on the SO/IO1 signal. This is referenced as a 1-1-1 command protocol for single bit width
instruction, single bit width address and modifier, single bit data.
Dual Output or Quad Output commands provide an address sent from the host on IO0. Data is returned to the host as bit pairs on
IO0 and IO1 or, four bit (nibble) groups on IO0, IO1, IO2, and IO3. This is referenced as 1-1-2 for Dual Output and 1-1-4 for Quad
Output command protocols.
Dual or Quad Input / Output (I/O) commands provide an address sent from the host as bit pairs on IO0 and IO1 or, four bit (nibble)
groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or, four bit (nibble) groups on IO0,
IO1, IO2, and IO3. This is referenced as 1-2-2 for Dual I/O and 1-4-4 for Quad I/O command protocols.
The FS-S Family also supports a QPI mode in which all information is transferred in 4-bit width, including the instruction, address,
modifier, and data. This is referenced as a 4-4-4 command protocol.
Commands are structured as follows:
 Each command begins with an eight bit (byte) instruction. However, some read commands are modified by a prior read
command, such that the instruction is implied from the earlier command. This is called Continuous Read Mode. When the device
is in continuous read mode, the instruction bits are not transmitted at the beginning of the command because the instruction is the
same as the read command that initiated the Continuous Read Mode. In Continuous Read mode the command will begin with the
read address. Thus, Continuous Read Mode removes eight instruction bits from each read command in a series of same type
read commands.
 The instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces
in the device. The address may be either a 24 bit or 32 bit, byte boundary, address.
 The Serial Peripheral Interface with Multiple IO provides the option for each transfer of address and data information to be done
one, two, or four bits in parallel. This enables a trade off between the number of signal connections (IO bus width) and the speed
of information transfer. If the host system can support a two or four bit wide IO bus the memory performance can be increased by
using the instructions that provide parallel two bit (dual) or parallel four bit (quad) transfers.
 In legacy SPI Multiple IO mode, the width of all transfers following the instruction are determined by the instruction sent. Following
transfers may continue to be single bit serial on only the SI or Serial Output (SO) signals, they may be done in two bit groups per
(dual) transfer on the IO0 and IO1 signals, or they may be done in 4 bit groups per (quad) transfer on the IO0-IO3 signals. Within
the dual or quad groups the least significant bit is on IO0. More significant bits are placed in significance order on each higher
numbered IO signal. Single bits or parallel bit groups are transferred in most to least significant bit order.
 In QPI mode, the width of all transfers, including instructions, is a 4-bit wide (quad) transfer on the IO0-IO3 signals.
 Dual I/O and Quad I/O read instructions send an instruction modifier called mode bits, following the address, to indicate that the
next command will be of the same type with an implied, rather than an explicit, instruction. The next command thus does not
provide an instruction byte, only a new address and mode bits. This reduces the time needed to send each command when the
same command type is repeated in a sequence of commands.
 The address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before
read data is returned to the host.
 Read latency may be zero to several SCK cycles (also referred to as dummy cycles).
Document Number: 002-03631 Rev. *C
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