BCM4356XKWBGT Datasheet, PDF (74/195 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1, FM Receiver, and Wireless Charging

BCM4356 Advance Data Sheet
PCI Express Interface
PCI Express Interface
The PCI Express (PCIe) core on the BCM4356 is a high-performance serial I/O interconnect that is protocol
compliant and electrically compatible with the PCI Express Base Specification v3.0 running at Gen1 speeds.
This core contains all the necessary blocks, including logical and electrical functional subblocks to perform PCIe
functionality and maintain high-speed links, using existing PCI system configuration software implementations
without modification.
Organization of the PCIe core is in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as
shown in Figure 31. A configuration or link management block is provided for enumerating the PCIe
configuration space and supporting generation and reception of System Management Messages by
communicating with PCIe layers.
Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication
between the host and BCM4356 device. The transmit side processes outbound packets whereas the receive
side processes inbound packets. Packets are formed and generated in the Transaction and Data Link Layer for
transmission onto the high-speed links and onto the receiving device. A header is added at the beginning to
indicate the packet type and any other optional fields.
Figure 31: PCI Express Layer Model
HW/SW Interface
HW/SW Interface
Transaction
Layer
Transaction
Layer
Data Link
Layer
Physical Layer
Logical Subblock
Electrical Subblock
TX
RX
Data Link
Layer
Physical Layer
Logical Subblock
Electrical Subblock
TX
RX
Broadcom^®
May 8, 2015 • 4356-DS103-R
BROADCOM CONFIDENTIAL
Page 73