BCM4356XKWBGT Datasheet, PDF (11/195 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1, FM Receiver, and Wireless Charging

BCM4356 Advance Data Sheet
List of Figures
List of Figures
Figure 1: Functional Block Diagram................................................................................................................... 1
Figure 2: BCM4356 Block Diagram ................................................................................................................. 17
Figure 3: Typical Power Topology for the BCM4356 ....................................................................................... 21
Figure 4: High-Level Functional Block Diagram for Wireless Charging ........................................................... 25
Figure 5: Power Receiver Unit ......................................................................................................................... 26
Figure 6: BCM59350 and BCM4356 Interface ................................................................................................. 27
Figure 7: Recommended Oscillator Configuration ........................................................................................... 28
Figure 8: Recommended Circuit to Use with an External Reference Clock..................................................... 29
Figure 9: Startup Signaling Sequence ............................................................................................................. 39
Figure 10: CVSD Decoder Output Waveform Without PLC............................................................................. 41
Figure 11: CVSD Decoder Output Waveform After Applying PLC................................................................... 41
Figure 12: Functional Multiplex Data Diagram................................................................................................. 47
Figure 13: PCM Timing Diagram (Short Frame Sync, Master Mode) .............................................................. 48
Figure 14: PCM Timing Diagram (Short Frame Sync, Slave Mode) ................................................................ 49
Figure 15: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 50
Figure 16: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 51
Figure 17: PCM Burst Mode Timing (Receive Only, Short Frame Sync) ......................................................... 52
Figure 18: PCM Burst Mode Timing (Receive Only, Long Frame Sync) ......................................................... 53
Figure 19: USB Compounded Device Configuration ....................................................................................... 54
Figure 20: USB Full-Speed Timing .................................................................................................................. 56
Figure 21: UART Timing .................................................................................................................................. 58
Figure 22: I²S Transmitter Timing .................................................................................................................... 61
Figure 23: I²S Receiver Timing........................................................................................................................ 61
Figure 24: Example Blend/Switch Usage......................................................................................................... 64
Figure 25: Example Blend/Switch Separation.................................................................................................. 65
Figure 26: Example Soft Mute Characteristic .................................................................................................. 65
Figure 27: Broadcom GCI Mode LTE Coexistence Interface........................................................................... 68
Figure 28: Legacy 3-Wire LTE Coexistence Interface ..................................................................................... 69
Figure 29: Signal Connections to SDIO Host (SD 4-Bit Mode) ........................................................................ 72
Figure 30: Signal Connections to SDIO Host (SD 1-Bit Mode) ........................................................................ 72
Figure 31: PCI Express Layer Model ............................................................................................................... 73
Figure 32: WLAN MAC Architecture ................................................................................................................ 76
Figure 33: WLAN PHY Block Diagram............................................................................................................. 81
Figure 34: Radio Functional Block Diagram (Core 0) ...................................................................................... 83
Figure 35: BCM4356 A2 WLBGA BALL MAP; 12 × 18 Array; 192 Balls; Bottom View (Balls Facing Up)....... 85
Broadcom^®
May 8, 2015 • 4356-DS103-R
BROADCOM CONFIDENTIAL
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