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BCM4356XKWBGT Datasheet, PDF (70/195 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1, FM Receiver, and Wireless Charging
BCM4356 Advance Data Sheet
Figure 28: Legacy 3-Wire LTE Coexistence Interface
UART Interface
WLAN
GCI_GPIO_2
GCI_GPIO_1
GCI
GCI_GPIO_0
WCN_PRIORITY
MWS_RX, LTE_PRIORITY
LTE_FRAME_SYNC
BT/FM
BCM4356
LTE/IC
Note: OR’ing to generate WCN_PRIORITY FOR ERCX_TXCONF or BT_RX_PRIORITY is achieved by
setting the GPIO mask registers appropriately.
UART Interface
One 2-wire UART interface can be enabled by software as an alternate function on GPIO pins. Refer to
Table 26: “GPIO Alternative Signal Functions,” on page 121. Provided primarily for debugging during
development, this UART enables the BCM4356 to operate as RS-232 data termination equipment (DTE) for
exchanging and managing data with other serial devices. It is compatible with the industry standard 16550
UART, and provides a FIFO size of 64 × 8 in each direction.
JTAG Interface
The BCM4356 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and
PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist
customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is
highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs.
Refer to Table 26: “GPIO Alternative Signal Functions,” on page 121 for JTAG pin assignments.
Broadcom®
May 8, 2015 • 4356-DS103-R
BROADCOM CONFIDENTIAL
Page 69