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BCM4356XKWBGT Datasheet, PDF (31/195 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac 2×2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1, FM Receiver, and Wireless Charging | |||
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BCM4356 Advance Data Sheet
External Frequency Reference
Table 3: Crystal Oscillator and External ClockâRequirements and Performance (Cont.)
Crystala
External Frequency
Referenceb, c
Parameter
Conditions/Notes
Min. Typ. Max. Min. Typ. Max. Units
Drive level
External crystal must be able to 200 â
â
â
â
tolerate this drive level.
â μW
Input impedance Resistive
(WRF_XTAL_IN) Capacitive
â
â
â 30 100
â kâ¦
â
â 7.5 â
â
7.5 pF
WRF_XTAL_IN
Input low level
DC-coupled digital signal
â
â
â
0
â
0.2 V
WRF_XTAL_IN
Input high level
DC-coupled digital signal
â
â
â 1.0 â 1.26 V
WRF_XTAL_IN
input voltage
(see Figure 8)
AC-coupled analog signal
â
â
â 400 â
1200 mVp-p
Duty cycle
37.4 MHz clock
â
â
â 40 50
60 %
Phase Noiseg
37.4 MHz clock at 10 kHz offset â
â
â
â
â â129 dBc/Hz
(IEEE 802.11b/g) 37.4 MHz clock at 100 kHz offset â
â
â
â
â â136 dBc/Hz
Phase Noiseg
37.4 MHz clock at 10 kHz offset â
â
â
â
â â137 dBc/Hz
(IEEE 802.11a) 37.4 MHz clock at 100 kHz offset â
â
â
â
â â144 dBc/Hz
Phase Noiseg
37.4 MHz clock at 10 kHz offset â
â
â
â
â â134 dBc/Hz
(IEEE 802.11n, 37.4 MHz clock at 100 kHz offset â
â
â
â
â â141 dBc/Hz
2.4 GHz)
Phase Noiseg,h 37.4 MHz clock at 10 kHz offset â
â
â
â
â â142 dBc/Hz
(IEEE 802.11n, 37.4 MHz clock at 100 kHz offset â
â
â
â
â â149 dBc/Hz
5 GHz)
Phase Noiseg
37.4 MHz clock at 10 kHz offset â
â
â
â
â â150 dBc/Hz
(IEEE 802.11ac, 37.4 MHz clock at 100 kHz offset â
â
â
â
â â157 dBc/Hz
5 GHz)
a. (Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT.
b. See âExternal Frequency Referenceâ on page 29 for alternate connection methods.
c. For a clock reference other than 37.4 MHz, 20 Ã log10(f/ 37.4) dB should be added to the limits, where f = the
reference clock frequency in MHz.
d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high.
Note that 52 MHz is not an autoâdetected frequency using the LPO clock.
e. The frequency step size is approximately 80 Hz resolution.
f. It is the responsibility of the equipment designer to select oscillator components that comply with these
specifications.
g. Assumes that external clock has a flat phase noise response above 100 kHz.
h. If the reference clock frequency is <35 MHz the phase noise requirements must be tightened by an additional
2 dB.
Broadcom®
May 8, 2015 ⢠4356-DS103-R
BROADCOM CONFIDENTIAL
Page 30
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