BCM43455XKUBGT Datasheet, PDF (58/159 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/ Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM43455 Preliminary Data Sheet
Figure 17: UART Timing
BT_UART_CTS_N
1
BT_UART_TXD
Midpoint of STOP bit
BT_UART_RXD
3
BT_UART_RTS_N
I²S Interface
2
Midpoint of STOP bit
Table 13: UART Timing Specifications
Ref Characteristics
Min.
1 Delay time, BT_UART_CTS_N low to BT_UART_TXD valid –
2 Setup time, BT_UART_CTS_N high before midpoint of stop –
bit
3 Delay time, midpoint of stop bit to BT_UART_RTS_N high –
Typ.
–
–
–
Max.
1.5
0.5
0.5
Unit
Bit periods
Bit periods
Bit periods
I²S Interface
The BCM43455 supports an I²S digital audio port for Bluetooth audio. The I²S signals are:
• I²S clock: I²S SCK
• I²S Word Select: I²S WS
• I²S Data Out: I²S SDO
• I²S Data In: I²S SDI
I²S SCK and I²S WS become outputs in master mode and inputs in slave mode, while I²S SDO always stays
as an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data
is aligned with the MSB of the I²S bus, per the I²S specification. The MSB of each data word is transmitted one
bit clock cycle after the I²S WS transition, synchronous with the falling edge of bit clock. Left-channel data is
transmitted when I²S WS is low, and right-channel data is transmitted when I²S WS is high. Data bits sent by
the BCM43455 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on
the rising edge of I2S_SSCK.
The clock rate in master mode is either of the following:
48 kHz x 32 bits per frame = 1.536 MHz
48 kHz x 50 bits per frame = 2.400 MHz
The master clock is generated from the input reference clock using a N/M clock divider. In the slave mode, any
clock rate is supported to a maximum of 3.072 MHz.
Broadcom^®
November 5, 2015 • 43455-DS109-R
BROADCOM CONFIDENTIAL
Page 57