BCM43455XKUBGT Datasheet, PDF (142/159 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/ Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM43455 Preliminary Data Sheet
SDIO High-Speed Mode Timing
SDIO high-speed mode timing is shown by the combination of Figure 35 and Table 54.
Figure 35: SDIO Bus Timing (High-Speed Mode)
50% VDD
SDIO_CLK
f_PP
t_WL
t_WH
Input
t_THL
t_ISU
t_TLH
t_IH
SDIO Timing
Output
t_ODLY
t_OH
Table 54: SDIO Bus Timing^a Parameters (High-Speed Mode)
Parameter
Symbol Minimum Typical
SDIO CLK (all values are referred to minimum VIH and maximum VIL^b)
Frequency – Data Transfer Mode
fPP
0
–
Frequency – Identification Mode
fOD
0
–
Clock low time
tWL
7
–
Clock high time
tWH
7
–
Clock rise time
tTLH
–
–
Clock low time
tTHL
–
–
Inputs: CMD, DAT (referenced to CLK)
–
–
–
Input setup Time
tISU
6
–
Input hold Time
tIH
2
–
Outputs: CMD, DAT (referenced to CLK)
–
–
–
Output delay time – Data Transfer Mode
tODLY
–
–
Output hold time
tOH
2.5
–
Total system capacitance (each line)
CL
–
–
a. Timing is based on CL  40 pF load on CMD and Data.
b. Min (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.
Maximum Unit
50
MHz
400
kHz
–
ns
–
ns
3
ns
3
ns
–
–
–
ns
–
ns
–
–
14
ns
–
ns
40
pF
Broadcom^®
November 5, 2015 • 43455-DS109-R
BROADCOM CONFIDENTIAL
Page 141