BCM43455XKUBGT Datasheet, PDF (54/159 Pages) Cypress Semiconductor – Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/ Radio with Integrated Bluetooth 4.1 and FM Receiver

BCM43455 Preliminary Data Sheet
PCM Interface
Long Frame Sync, Slave Mode
Figure 14: PCM Timing Diagram (Long Frame Sync, Slave Mode)
PC M _BC LK
PCM_SYNC
PC M _O U T
6
P C M _IN
1
4
5
B it 0
B it 0
Bit 1
Bit 1
2
3
9
7
H IG H IM PE D AN C E
8
Table 9: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)
Reference Characteristics
1
PCM bit clock frequency
2
PCM bit clock LOW
3
PCM bit clock HIGH
4
PCM_SYNC setup
5
PCM_SYNC hold
6
PCM_OUT delay
7
PCM_IN setup
8
PCM_IN hold
9
Delay from rising edge of PCM_BCLK during last bit
period to PCM_OUT becoming high impedance
Minimum
–
41
41
8
8
0
8
8
0
Typical
–
–
–
–
–
–
–
–
–
Maximum Unit
12
MHz
–
ns
–
ns
–
ns
–
ns
25
ns
–
ns
–
ns
25
ns
Broadcom^®
November 5, 2015 • 43455-DS109-R
BROADCOM CONFIDENTIAL
Page 53