BCM20713A1KUFBXG Datasheet, PDF (56/65 Pages) Cypress Semiconductor – Single-Chip Bluetooth Transceiver and Baseband Processor

BCM20713 Preliminary Data Sheet
Timing and AC Characteristics
Table 26: PCM Interface Timing Specifications (Long Frame Synchronization, Slave Mode)
Reference
1
2
3
4
5
6
7
8
9
10
Characteristics
Minimum
PCM bit clock frequency.
128
PCM bit clock HIGH time.
209
PCM bit clock LOW time.
209
Setup time for PCM_SYNC before falling edge of
50
PCM_BCLK during first bit time.
Hold time for PCM_SYNC after falling edge of PCM_BCLK 10
during second bit period. (PCM_SYNC may go low any time
from second bit period to last bit period).
Delay from rising edge of PCM_BCLK or PCM_SYNC
–
(whichever is later) to data valid for first bit on PCM_OUT.
Hold time of PCM_OUT after PCM_BCLK falling edge. –
Setup time for PCM_IN before PCM_BCLK falling edge. 50
Hold time for PCM_IN after PCM_BCLK falling edge.
10
Delay from falling edge of PCM_BCLK or PCM_SYNC –
(whichever is later) during last bit in slot to PCM_OUT
becoming high impedance.
Maximum Unit
2048
kHz
–
ns
–
ns
–
ns
–
ns
50
ns
175
ns
–
ns
–
ns
100
ns
Figure 16: PCM Interface Timing (Long Frame Synchronization, Slave Mode)
PCM_BCLK
PCM_SYNC
1
4
2
3
5
6
PCM_OUT
Bit 0
PCM_IN
Bit 0
7
Bit 1
8
9
Bit 1
10
Bit 15
HIGH
IMPEDENCE
Bit 15
Broadcom^®
December 21, 2015 • 20713-DS102-R
Single-Chip Bluetooth Transceiver and Baseband Processor
Page 55
BROADCOM CONFIDENTIAL