BCM20713A1KUFBXG Datasheet, PDF (30/65 Pages) Cypress Semiconductor – Single-Chip Bluetooth Transceiver and Baseband Processor

BCM20713 Preliminary Data Sheet
SPI
Normally, the UART baud rate is set by a configuration record downloaded after reset or by automatic baud rate
detection. The host does not need to adjust the baud rate. Support for changing the baud rate during normal
HCI UART operation is provided through a vendor-specific command.
The BCM20713 UART operates with the host UART correctly, provided the combined baud rate error of the two
devices is within ±2%.
HCI 3-Wire Transport (UART H5)
The BCM20713 supports H5 UART transport for serial UART communications. H5 reduces the number of signal
lines required by eliminating CTS and RTS, when compared to H4. In addition, in-band sleep signaling is
supported over the same interface so that the 4-wire UART and the 2-wire sleep signaling interface can be
reduced to a 2-wire UART interface, saving four I/Os on the host.
H5 requires the use of an external LPO. CTS must be pulled low.
SPI
The BCM20713 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates
may be possible. The physical interface between the SPI master and the BCM20713 consists of the four SPI
signals (SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO) and one interrupt signal (SPI_INT). The BCM20713 can be
configured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be
configured to drive an active-low or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO
data lines can be configured as either little-endian or big-endian. Additionally, proprietary sleep mode, half-
duplex handshaking is implemented between the SPI master and the BCM20713.
SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the
middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop
the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented
in higher layer protocols.
Broadcom^®
December 21, 2015 • 20713-DS102-R
Single-Chip Bluetooth Transceiver and Baseband Processor
Page 29
BROADCOM CONFIDENTIAL