CY8C3245LTI-144T Datasheet, PDF (53/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
7.7 I²C
PSoC includes a single fixed-function I²C peripheral. Additional
I²C interfaces can be instantiated using Universal Digital Blocks
(UDBs) in PSoC Creator, as required.
The I²C peripheral provides a synchronous two-wire interface
designed to interface the PSoC device with a two-wire I²C serial
communication bus. It is compatible^[13] with I²C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I²C bus
I/O may be implemented with GPIO or SIO in open-drain modes.
To eliminate the need for excessive CPU intervention and
overhead, I²C specific support is provided for status detection
and generation of framing bits. I²C operates as a slave, a master,
or multimaster (Slave and Master)^[14]. In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I²C interfaces through the
DSI routing and allows direct connections to any GPIO or SIO
pins.
I²C provides hardware address detect of a 7-bit address without
CPU intervention. Additionally the device can wake from
low-power modes on a 7-bit hardware address match. If wakeup
functionality is required, I2C pin connections are limited to one
of two specific pairs of SIO pins. See descriptions of SCL and
SDA pins in Pin Descriptions on page 12.
I²C features include:
 Slave and Master, Transmitter, and Receiver operation
 Byte processing for low CPU overhead
 Interrupt or polling CPU interface
 Support for bus speeds up to 1 Mbps
 7 or 10-bit addressing (10-bit addressing requires firmware
support)
 SMBus operation (through firmware support – SMBus
supported in hardware in UDBs)
 7-bit hardware address compare
 Wake from low-power modes on address match
 Glitch filtering (active and alternate-active modes only)
Data transfers follow the format shown in Figure 7-16. After the
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
indicates a request for data (READ). A data transfer is always
terminated by a STOP condition (P) generated by the master.
Figure 7-16. I²C Complete Transfer Timing
SDA
SCL
START
Condition
1-7
ADDRESS
8
9
R/W
ACK
1-7
8
DATA
9
ACK
1-7
8
DATA
9
ACK
STOP
Condition
7.7.1 External Electrical Connections
As Figure 7-17 shows, the I²C bus requires external pull-up
resistors (R_P). These resistors are primarily determined by the
supply voltage, bus speed, and bus capacitance. For detailed
information on how to calculate the optimum pull-up resistor
value for your design, we recommend using the UM10204
I2C-bus specification and user manual Rev 6, or newer, available
from the NXP website at www.nxp.com.
Notes
13. The I²C peripheral is non-compliant with the NXP I2C specification in the following areas: analog glitch filter, I/O VOL/IOL, I/O hysteresis. The I²C Block has a digital
glitch filter (not available in sleep mode). The Fast-mode minimum fall-time specification can be met by setting the I/Os to slow speed mode. See the I/O Electrical
Specifications in “Inputs and Outputs” section on page 76 for details.
14.
IF^{2iCxecdo-bmlopcokneI2}nCt
does not support undefined
should be used instead.
bus
conditions,
nor
does
it
support
Repeated
Start
in
Slave
mode.
These
conditions
should
be
avoided,
or
the
UDB-based
Document Number: 001-56955 Rev. *Y
Page 53 of 128