CY8C3245LTI-144T Datasheet, PDF (21/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
Figure 4-2. Interrupt Processing Timing Diagram
1
2
3
4
5
6
7
8
9
10
CLK
INT_INPUT
PEND
POST
IRQ
ACTIVE_INT_NUM
(#10)
INT_VECT_ADDR
Arrival of new Interrupt
Pend bit is set on next clock active edge
POST and PEND bits cleared after IRQ is sleared
Interrupt is posted to ascertain the priority
Interrupt request sent to core for processing
IRQ cleared after receiving IRA
The active interrupt
NA
0x0010
number is posted to core
NA
The active interrupt ISR
address is posted to core
NA
11
S
S
S
S
S
S
S
S
S
IRA
S
IRC
Interrupt generation and posting to CPU
CPU Response
Int. State
Clear
Completing current instruction and branching to vector address
S
Complete ISR and return
0x0000
TIME
Notes
1: Interrupt triggered asynchronous to the clock
2: The PEND bit is set on next active clock edge to indicate the interrupt arrival
3: POST bit is set following the PEND bit
4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)
5: ISR address is posted to CPU core for branching
6: CPU acknowledges the interrupt request
7: ISR address is read by CPU for branching
8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)
11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status
The total interrupt latency (ISR execution)
= POST + PEND + IRQ + IRA + Completing current instruction and branching
= 1+1+1+2+7 cycles
= 12 cycles
Document Number: 001-56955 Rev. *Y
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