CY8C3245LTI-144T Datasheet, PDF (33/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
6.2.1 Power Modes
PSoC 3 devices have four different power modes, as shown in
Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
 Active
 Alternate Active
 Sleep
 Hibernate
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins. Figure 6-5 illustrates the allowable transitions between
power modes. Sleep and hibernate modes should not be entered
until all VDDIO supplies are at valid voltage levels.
Table 6-2. Power Modes
Power Modes
Description
Entry Condition Wakeup Source Active Clocks
Active
Primary mode of operation, all Wakeup, reset, Any interrupt
peripherals available (program- manual register
mable)
entry
Any
(programmable)
Alternate
Active
Sleep
Similar to Active mode, and is Manual register
typically configured to have
entry
fewer peripherals active to
reduce power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
All subsystems automatically Manual register
disabled
entry
Any interrupt
Any
(programmable)
Comparator,
ILO/kHzECO
PICU, I²C, RTC,
CTW, LVD
Hibernate
All subsystems automatically Manual register
disabled
entry
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
PICU
Regulator
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
All regulators available.
Digital and analog
regulators can be disabled
if external regulation used.
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Only hibernate regulator
active.
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Active
Alternate
Active
Sleep
Wakeup
Time
–
–
<15 µs
Hibernate <100 µs
Current
(typ)
1.2 mA^[11]
–
1 µA
200 nA
Code
Execution
Yes
User
defined
No
No
Digital
Resources
All
All
I²C
None
Analog
Resources
All
All
Clock Sources
Available
All
All
Comparator ILO/kHzECO
None
None
Wakeup Sources
–
–
Comparator,
PICU, I²C, RTC,
CTW, LVD
PICU
Reset
Sources
All
All
XRES, LVD,
WDR
XRES
Note
11. Bus clock off. Execute from cache at 6 MHz. See Table 11-2 on page 68.
Document Number: 001-56955 Rev. *Y
Page 33 of 128