CY8C3245LTI-144T Datasheet, PDF (106/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
11.8.3 Interrupt Controller
Table 11-61. Interrupt Controller AC Specifications
Parameter
Description
Conditions
Min
Delay from interrupt signal input to ISR Includes worse case completion of –
code execution from ISR code
longest instruction DIV with 6
cycles
Typ Max Units
–
25 Tcy CPU
11.8.4 JTAG Interface
TCK
Figure 11-57. JTAG Interface Timing
(1/f_TCK)
T_TDI_setup T_TDI_hold
TDI
TDO
TMS
T_TMS_setup T_TMS_hold
T_TDO_valid
T_TDO_hold
Table 11-62. JTAG Interface AC Specifications^[65]
Parameter
Description
f_TCK
TCK frequency
T_TDI_setup
T_TMS_setup
T_TDI_hold
T_TDO_valid
T_TDO_hold
TDI setup before TCK high
TMS setup before TCK high
TDI, TMS hold after TCK high
TCK low to TDO valid
TDO hold after TCK high
Conditions
3.3 V  V_DDD  5 V
1.71 V  V_DDD < 3.3 V
T = 1/f_TCK max
T = 1/f_TCK max
T = 1/f_TCK max
Min Typ
–
–
–
–
(T/10) – 5 –
T/4
–
T/4
–
–
–
T/4
–
Max
14^[66]
7^[66]
–
–
–
2T/5
–
Units
MHz
MHz
ns
Notes
65. Based on device characterization (Not production tested).
66. f_TCK must also be no more than 1/3 CPU clock frequency.
Document Number: 001-56955 Rev. *Y
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