CY8C28243_09 Datasheet, PDF (40/65 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip

PRELIMINARY
CY8C28xxx
Figure 8. Basic Switch Mode Pump Circuit
D1
+
V_BAT
L₁
Battery
Vdd
V _PUMP
C1
SMP
PSoC ^TM
Vss
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T_A ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T_A ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 21. 5V DC Analog Reference Specifications for High Power
Symbol
Description
Min
V_BG5
–
–
–
–
–
–
Bandgap Voltage Reference 5V
1.28
AGND = Vdd/2^[16]
Vdd/2 - 0.02
AGND = 2 x BandGap^[16]
2.52
AGND = P2[4] (P2[4] = Vdd/2)^[16]
P2[4] - 0.013
AGND = BandGap^[16]
1.27
AGND = 1.6 x BandGap^[16]
2.03
AGND Block to Block Variation (AGND = Vdd/2)^[16] -0.034
–
RefHi = Vdd/2 + BandGap
Vdd/2 + 1.21
–
RefHi = 3 x BandGap
3.75
–
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
P2[6] + 2.478
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
P2[4] + 1.218
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] + P2[6] -
0.058
–
RefHi = 2 x BandGap
2.50
–
RefHi = 3.2 x BandGap
4.02
–
RefLo = Vdd/2 – BandGap
Vdd/2 - 1.369
–
RefLo = BandGap
1.20
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
2.489 - P2[6]
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
P2[4] - 1.368
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) P2[4] - P2[6] -
0.042
Typ
1.30
Vdd/2
2.60
P2[4]
1.3
2.08
0.000
Vdd/2 + 1.3
3.9
P2[6] + 2.6
P2[4] + 1.3
P2[4] + P2[6]
2.60
4.16
Vdd/2 - 1.30
1.30
2.6 - P2[6]
P2[4] - 1.30
P2[4] - P2[6]
Max
1.32
Vdd/2 + 0.02
2.72
P2[4] + 0.013
1.34
2.13
0.034
Vdd/2 + 1.382
4.05
P2[6] + 2.722
P2[4] + 1.382
P2[4] + P2[6] +
0.058
2.70
4.29
Vdd/2 - 1.231
1.40
2.711 - P2[6]
P2[4] - 1.232
P2[4] - P2[6] +
0.042
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Note
16. AGND tolerance includes the offsets of the local buffer in the PSoC block.
Document Number: 001-48111 Rev. *D
Page 40 of 65
[+] Feedback