CY8C28243_09 Datasheet, PDF(18/65 Page) Cypress Semiconductor – PSoC Programmable System-on-Chip

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

CY8C28243_09 Datasheet, PDF (18/65 Pages) Cypress Semiconductor – PSoC Programmable System-on-Chip

◁

PRELIMINARY

CY8C28xxx

CY8C28x03 Register Map Bank 1 Table: Configuration Space

Name

Addr (1,Hex) Access

Name

Addr (1,Hex) Access

PRT0DM0

00

RW DBC20FN

40

RW

PRT0DM1

01

RW DBC20IN

41

RW

PRT0IC0

02

RW DBC20OU

42

RW

PRT0IC1

03

RW DBC20CR1

43

RW

PRT1DM0

04

RW DBC21FN

44

RW

PRT1DM1

05

RW DBC21IN

45

RW

PRT1IC0

06

RW DBC21OU

46

RW

PRT1IC1

07

RW DBC21CR1

47

RW

PRT2DM0

08

RW DCC22FN

48

RW

PRT2DM1

09

RW DCC22IN

49

RW

PRT2IC0

0A

RW DCC22OU

4A

RW

PRT2IC1

0B

RW DCC22CR1

4B

RW

PRT3DM0

0C

RW DCC23FN

4C

RW

PRT3DM1

0D

RW DCC23IN

4D

RW

PRT3IC0

0E

RW DCC23OU

4E

RW

PRT3IC1

0F

RW DCC23CR1

4F

RW

PRT4DM0

10

RW

50

PRT4DM1

11

RW

51

PRT4IC0

12

RW

52

PRT4IC1

13

RW

53

PRT5DM0

14

RW

54

PRT5DM1

15

RW

55

PRT5IC0

16

RW

56

PRT5IC1

17

RW

57

18

58

19

59

1A

5A

1B

5B

1C

5C

1D

5D

1E

5E

1F

5F

DBC00FN

20

RW

60

DBC00IN

21

RW

61

DBC00OU

22

RW

62

DBC00CR1

23

RW

63

DBC01FN

24

RW

64

DBC01IN

25

RW

65

DBC01OU

26

RW

66

DBC01CR1

27

RW

67

DCC02FN

28

RW

68

DCC02IN

29

RW

69

DCC02OU

2A

RW

6A

DCC02CR1

2B

RW I2C1_CFG

6B

RW

DCC03FN

2C

RW TMP_DR0

6C

RW

DCC03IN

2D

RW TMP_DR1

6D

RW

DCC03OU

2E

RW TMP_DR2

6E

RW

DCC03CR1

2F

RW TMP_DR3

6F

RW

DBC10FN

30

RW

70

DBC10IN

31

RW SADC_TSCR0

71

RW

DBC10OU

32

RW SADC_TSCR1

72

RW

DBC10CR1

33

RW

73

DBC11FN

34

RW

74

DBC11IN

35

RW

75

DBC11OU

36

RW

76

DBC11CR1

37

RW

77

DCC12FN

38

RW

78

DCC12IN

39

RW

79

DCC12OU

3A

RW

7A

DCC12CR1

3B

RW

7B

DCC13FN

3C

RW

7C

DCC13IN

3D

RW

7D

DCC13OU

3E

RW

7E

DCC13CR1

3F

RW

7F

Blank fields are Reserved and should not be accessed.

# Access is bit specific.

Name

Addr (1,Hex) Access

Name

Addr (1,Hex)

80

RDI2RI

C0

SADC_TSCMPL

81

RW RDI2SYN

C1

SADC_TSCMPH

82

RW RDI2IS

C2

83

RDI2LT0

C3

84

RDI2LT1

C4

85

RDI2RO0

C5

86

RDI2RO1

C6

87

RDI2DSM

C7

88

C8

89

C9

8A

CA

8B

CB

8C

CC

8D

CD

8E

CE

8F

CF

90

GDI_O_IN

D0

91

GDI_E_IN

D1

92

GDI_O_OU

D2

93

GDI_E_OU

D3

94

D4

95

D5

96

D6

97

D7

98

D8

99

D9

9A

DA

9B

DB

9C

DC

9D

OSC_GO_EN

DD

9E

OSC_CR4

DE

9F

OSC_CR3

DF

GDI_O_IN_CR

A0

RW OSC_CR0

E0

GDI_E_IN_CR

A1

RW OSC_CR1

E1

GDI_O_OU_CR

A2

RW OSC_CR2

E2

GDI_E_OU_CR

A3

RW VLT_CR

E3

RTC_H

A4

RW VLT_CMP

E4

RTC_M

A5

RW

E5

RTC_S

A6

RW

E6

RTC_CR

A7

RW

E7

SADC_CR0

A8

RW IMO_TR

E8

SADC_CR1

A9

RW ILO_TR

E9

SADC_CR2

AA

RW BDG_TR

EA

SADC_CR3

AB

RW ECO_TR

EB

SADC_CR4

AC

RW

EC

I2C0_ADDR

AD

RW

ED

I2C1_ADDR

AE

RW

EE

AMUX_CLK

AF

RW

EF

RDI0RI

B0

RW

F0

RDI0SYN

B1

RW

F1

RDI0IS

B2

RW

F2

RDI0LT0

B3

RW

F3

RDI0LT1

B4

RW

F4

RDI0RO0

B5

RW

F5

RDI0RO1

B6

RW

F6

RDIODSM

B7

RW CPU_F

F7

RDI1RI

B8

RW

F8

RDI1SYN

B9

RW

F9

RDI1IS

BA

RW FLS_PR1

FA

RDI1LT0

BB

RW

FB

RDI1LT1

BC

RW

FC

RDI1RO0

BD

RW

FD

RDI1RO1

BE

RW CPU_SCR1

FE

RDI1DSM

BF

RW CPU_SCR0

FF

*Address has a dual purpose, see âMapping Exceptionsâ on page 251

Access

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RW

RL

RW

#

#

Document Number: 001-48111 Rev. *D

Page 18 of 65

[+] Feedback

▷