W195B Datasheet, PDF (4/13 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic

PRELIMINARY
W195B
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 100-MHz
CPU 100 Period
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC
Hub-PC
SDRAM 100 Period
Figure 3. Group Offset Waveforms (100.2 CPU Clock, 100.2 SDRAM Clock)
Power Down Control
W195B provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
0ns
1
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
25ns
50ns
2
75ns
Center
Figure 4. PWRDWN# Timing Diagram^{[2, 3, 4, 5]}
Notes:
2. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the next HIGH-to-LOW
transition.
3. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W195B.
4. The shaded sections on the SDRAM, REF, and USB clocks indicate “don’t care” states.
5. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
4