W195B Datasheet, PDF (1/13 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic

PRELIMINARY
W195B
Frequency Generator for Integrated Core Logic
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Two copies of CPU clocks
• Nine copies of SDRAM clocks
• Eight copies of PCI clock
• One copy of synchronous APIC clock
• Two copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• One copy of selectable 24- or 48-MHz clock
• One copy of double strength 14.31818-MHz reference
clock
• Power-down control
• I²C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
APIC, 48MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: .................................................. 500 ps
CPU, 3V66 Output Skew: ........................................... 175 ps
SDRAM, APIC, 48MHz Output Skew: ........................ 250 ps
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@100 MHz): ..................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns
PCI to APIC Skew: ....................................................± 0.5 ns
Table 1. Frequency Selections
FS3 FS2 FS1 FS0 CPU SDRAM 3V66 PCI APIC
1 1 1 1 133.6 133.6 66.8 33.4 16.7
1110
Reserved
1 1 0 1 100.2 100.2 66.8 33.4 16.7
1 1 0 0 66.8 100.2 66.8 33.4 16.7
1 0 1 1 105 105 70 35 17.5
1 0 1 0 110 110 73.3 36.7 18.3
1 0 0 1 114 114 76 38 19
1 0 0 0 119 119 79.3 39.7 19.8
0 1 1 1 124 124 82.7 41.3 20.7
0 1 1 0 129 129 64.5 32.3 16.1
0 1 0 1 95
95 63.3 31.7 15.8
0 1 0 0 138 138 69 34.5 17.3
0 0 1 1 150 150 75 37.5 18.8
0 0 1 0 75 113 75 37.5 18.8
0 0 0 1 90
90
60 30 15
0 0 0 0 83.3 125 83.3 41.7 20.8
Block Diagram
X1
XTAL
X2
OSC
PLL REF FREQ
SDATA
SCLK
FS3*
FS2*
FS1*
FS0*
I²C
Logic
Divider,
Delay,
and
Phase
Control
Logic
PLL 1
PWRDWN#
PLL2
/2
VDDQ3
REF2X/FS3*
VDDQ2
CPU0:1
2
APIC
VDDQ3
3V66_0:1
2
PCI0/FS0*
PCI1/FS1*
PCI2/FS2*
PCI3:7
5
SDRAM0:8
9
VDDQ3
48MHz_0:1
2
SI0/24_48#MHz*
[1]
Pin Configuration
REF2x/FS3* 1
VDDQ3 2
X1 3
X2 4
GND 5
VDDQ3 6
3V66_0 7
3V66_1 8
GND 9
FS0*/PCI0 10
FS1^/PCI1 11
FS2*/PCI2 12
GND 13
PCI3 14
PCI4 15
VDDQ3 16
PCI5 17
PCI6 18
PCI7 19
GND 20
48MHz_0 21
48MHz_1 22
SI0/24_48#MHz* 23
VDDQ3 24
48 VDDQ2
47 APIC
46 VDDQ2
45 CPU0
44 CPU1
43 GND
42 VDDQ3
41 SDRAM0
40 SDRAM1
39 SDRAM2
38 GND
37 SDRAM3
36 SDRAM4
35 SDRAM5
34 VDDQ3
33 SDRAM6
32 SDRAM7
31 SDRAM8
30 GND
29 PWRDWN#*
28 SCLK
27 VDDQ3
26 GND
25 SDATA
Note:
1. Internal 250K pull-up or pull down resistors present on inputs
marked with * or ^ respectively. Design should not rely solely on
internal pull-up or pull down resistor to set I/O pins HIGH or LOW
respectively.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **