W195B Datasheet, PDF (2/13 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic

PRELIMINARY
W195B
Pin Definitions
Pin Name
REF2x/FS3
Pin No.
1
X1
3
X2
4
PCI0/FS0
10
PCI1/FS1
11
PCI2/FS2
12
PCI3:7
3V66_0:1
14, 15, 17, 18,
19
7,8
48MHz_0:1
SIO/
24_48#MHz
21, 22
23
PWRDWN#
29
CPU0:1
45, 44
SDRAM0:8,
APIC
41, 40, 39, 37,
36, 35, 33, 32,
31
47
SDATA
SCLK
VDDQ3
VDDQ2
25
28
2, 6, 16, 24, 27,
34, 42
46, 48
GND
5, 9, 13, 20, 26,
30, 38, 43
Pin
Type
I/O
I
I
I/O
I/O
I/O
O
O
O
I/O
I
O
O
Pin Description
Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock out-
put. This pin also serves as the select strap to determine device operating frequency
as described in Table 1.
Crystal Input: This pin has dual functions. It can be used as an external 14.318-
MHz crystal connection or as an external reference frequency input.
Crystal Output: An input connection for an external 14.318-MHz crystal connec-
tion. If using an external reference, this pin must be left unconnected.
PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin
doubles as the select strap to determine device operating frequency as described
in Table 1.
PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually
turned off via I²C interface.
66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled
by FS0:3 (see Table 1).
48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output.
Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device.
During power-up, it also serves as a selection strap. If it is sampled HIGH, the output
frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz.
Power Down Control: LVTTL-compatible input that places the device in power-
down mode when held LOW.
CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies
depending on the configuration of FS0:3. Voltage swing is set by V_DDQ2.
SDRAM Clock Outputs: 3.3V outputs for SDRAM. The operating frequency is
controlled by FS0:3 (see Table 1).
O Synchronous APIC Clock Outputs: Clock outputs running synchronous with the
PCI clock outputs. Voltage swing set by V_DDQ2.
I/O Data pin for I²C circuitry.
I Clock pin for I²C circuitry.
P 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buff-
ers, reference output buffers, and 48-MHz output buffers. Connect to 3.3V.
P 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Con-
nect to 2.5V or 3.3V.
G Ground Connections: Connect all ground pins to the common system ground
plane.
2