W195B Datasheet, PDF (3/13 Pages) Cypress Semiconductor – Frequency Generator for Integrated Core Logic

PRELIMINARY
W195B
W195B
Power-on
Reset
Timer
Output
Buffer
Output Three-state Hold
Output
Low
QD
Data
Latch
10 kΩ
Output Strapping Resistor
Series Termination Resistor
Clock Load
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W195B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architec-
ture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
Pin # 1, 10, 11, 12, 23 are dual-purpose l/O pins. Upon power-
up the pin acts as a logic input. An external 10-kΩ strapping
resistor should be used. Figure 1 shows a suggested method
for strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below tar-
get but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Offsets Among Clock Signal Groups
Figure 2 and Figure 3 represent the phase relationship among
the different groups of clock outputs from W195B when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,
respectively. It should be noted that when CPU clock is oper-
ating at 100 MHz, CPU clock output is 180 degrees out of
phase with SDRAM clock outputs.
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 66-MHz
CPU 66 Period
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC
Hub-PC
SDRAM 100 Period
Figure 2. Group Offset Waveforms (66.8 CPU Clock, 100.2 SDRAM Clock)
3