4000S Datasheet, PDF (3/35 Pages) Cypress Semiconductor – 32-bit MCU Subsystem

PSoC^® 4: PSoC 4000S
Family Datasheet
PSoC 4000S
Architecture
32- bit
AHB- Lite
System Resources
Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
Clock
Clock Control
WDT
ILO
IMO
Reset
Reset Control
XRES
Test
TestMode Entry
Digital DFT
Analog DFT
Figure 1. Block Diagram
CPU Subsystem
SWD/ TC
Cortex
M0+
48 MHz
FAST MUL
NVIC, IRQMUX
SPCIF
FLASH
32 KB
Read Accelerator
SRAM
4 KB
SRAM Controller
ROM
8 KB
ROM Controller
System Interconnect ( Single Layer AHB)
Peripherals
PCLK
Peripheral Interconnect (MMIO)
High Speed I/ O Matrix & 2x Programmable I/O
Power Modes
Active/ Sleep
DeepSleep
I/O Subsystem
36x GPIOs, LCD
PSoC 4000S devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4000S devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4000S family provides a level of security not
possible with multi-chip application solutions or with
microcontrollers. It has the following advantages:
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4000S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4000S allows the
customer to make.
■ Allows disabling of debug features
■ Robust flash protection
■ Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-00123 Rev. *I
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